Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology* on 90 nm Process Technology Specification Update

Specification Update 31

Q45.

Execution of IRET or INTn Instructions May Cause Unexpected System Behavior

Problem: There is a small window of time, requiring alignment of many internal micro architectural events, during

which the speculative execution of the IRET or INTn instructions in protected or IA-32e mode may

result in unexpected software or system behavior.

Implication: This erratum may result in unexpected instruction execution, events, interrupts or a system hang when

the IRET instruction is executed. The execution of the INTn instruction may cause debug breakpoints to

be missed.

Workaround: It is possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

Q46.

Checking of Page Table Base Address May Not Match the Address Bit Width

Supported by the Platform

Problem: If the page table base address, included in the page map level-4 table, page-directory pointer table, page-

directory table or page table, exceeds the physical address range supported by the platform (e.g. 36-bit)

and it is less than the implemented address range (e.g. 40-bit), the processor does not check if the

address is invalid.

Implication: If software sets such invalid physical address in those tables, the processor does not generate a page

fault (#PF) upon access to that virtual address, and the access results in an incorrect read or write. If

BIOS provides only valid physical address ranges to the operating system, this erratum will not occur.

Workaround: BIOS must provide valid physical address ranges to the operating system.

Status: For the steppings affected, see the Summary Tables of Changes.

Q47.

The IA32_MCi_STATUS MSR May Improperly Indicate That Additional MCA

Information May Have Been Captured

Problem: When a data parity error is detected and the bus queue is busy, the ADDRV and MISCV bits of the

IA32_MCi_STATUS register may be asserted even though the contents of the IA32_MCi_ADDR and

IA32_MCi_MISC MSRs were not properly captured.

Implication: If this erratum occurs, the MCA information captured in the IA32_MCi_ADDR and IA32_MCi_MISC

may not correspond to the reported machine-check error, even though the ADDRV and MISCV are

asserted.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.