Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology* on 90 nm Process Technology Specification Update

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Specification Update 29
Q37.
Incorrect Access Controls to MSR_LASTBRANCH_0_FROM_LIP MSR Registers
Problem: When an access is made to the MSR_LASTBRANCH_0_FROM_LIP MSR register, an expected #GP
fault may not happen.
Implication: A read of the MSR_LASTBRANCH_0_FROM_LIP MSR register may not cause a #GP fault.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
Q38.
Recursive Page Walks May Cause a System Hang
Problem: A page walk, accessing the same page table entry multiple times but at different levels of the page
table, which causes the page table entry to have its Access bit set may result in a system hang.
Implication: When this erratum occurs, the system may experience a hang.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
Q39.
WRMSR to bit[0] of IA32_MISC_ENABLE Register Changes Only One Logical
Processor on a Hyper-Threading Technology Enabled Processor
Problem: On an HT enabled processor, a write to the fast-strings feature bit[0] of IA32_MISC_ENABLE register
changes the setting for the current logical processor only.
Implication: Due to this erratum, the non-current logical processor may not update fast-strings feature bit[0] of
IA32_MISC_ENABLE register.
Workaround: BIOS may set the fast-strings enable bit on both logical processors to workaround this erratum. It is
possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
Q40.
Data Breakpoints on the High Half of a Floating Point Line Split May Not Be
Captured
Problem: When a floating point load which splits a 64-byte cache line gets a floating point stack fault, and a data
breakpoint register maps to the
high line of the floating point load, internal boundary conditions exist that may prevent the data
breakpoint from being captured.
Implication: When this erratum occurs, a data breakpoint will not be captured.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.