Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology* on 90 nm Process Technology Specification Update

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Specification Update 27
• When the reporting of errors is disabled for Machine Check Architecture (MCA) Bank 2 by setting all
MC2_CTL register bits to 0, uncorrectable errors should be logged in the IA32_MC2_STATUS
register but no machine-check exception should be generated. Uncorrectable loads on bank 2, which
would normally be logged in the IA32_MC2_STATUS register, are not logged.
• When one-half of a 64-byte instruction fetch from the L2 cache has an uncorrectable error and the
other 32-byte half of the same fetch from the L2 cache has a correctable error, the processor will
attempt to correct the correctable error but cannot proceed due to the uncorrectable error. When this
occurs the processor will hang.
• When an L1 cache parity error occurs, the cache controller logic should write the physical address of
the data memory location that produced that error into the IA32_MC1_ADDR REGISTER
(MC1_ADDR). In some instances of a parity error on a load operation that hits the L1 cache, the
cache controller logic may write the physical address from a subsequent load or store operation into
the IA32_MC1_ADDR register.
• When an error exists in the tag field of a cache line such that a request for ownership (RFO) issued by
the processor hits multiple tag fields in the L2 cache (the correct tag and the tag with the error) and
the accessed data also has a correctable error, the processor will correctly log the multiple tag match
error but will hang when attempting to execute the machine check exception handler.
• If a memory access receives a machine check error on both 64 byte halves of a 128-byte L2 cache
sector, the IA32_MC0_STATUS register records this event as multiple errors, i.e., the valid error bit
and the overflow error bit are both set indicating that a machine check error occurred while the results
of a previous error were in the error-reporting bank. The IA32_MC1_STATUS register should also
record this event as multiple errors but instead records this event as only one correctable error.
• The overflow bit should be set to indicate when more than one error has occurred. The overflow bit
being set indicates that more than one error has occurred. Because of this erratum, if any further
errors occur, the MCA overflow bit will not be updated, thereby incorrectly indicating only one error
has been received.
• If an I/O instruction (IN, INS, REP INS, OUT, OUTS, or REP OUTS) is being executed, and if the
data for this instruction becomes corrupted, the processor will signal a Machine Check Exception
(MCE). If the instruction is directed at a device that is powered down, the processor may also receive
an assertion of SMI#. Since MCEs have higher priority, the processor will call the MCE handler, and
the SMI# assertion will remain pending. However, while attempting to execute the first instruction of
the MCE handler, the SMI# will be recognized and the processor will attempt to execute the SMM
handler. If the SMM handler is successfully completed, it will attempt to restart the I/O instruction,
but will not have the correct machine state due to the call to the MCE handler. This can lead to
failure of the restart and shutdown of the processor.
• If PWRGOOD is de-asserted during a RESET# assertion causing internal glitches, the MCA registers
may latch invalid information.
• If RESET# is asserted, then de-asserted, and reasserted, before the processor has cleared the MCA
registers, then the information in the MCA registers may not be reliable, regardless of the state or
state transitions of PWRGOOD.
• If MCERR# is asserted by one processor and observed by another processor, the observing processor
does not log the assertion of MCERR#. The Machine Check Exception (MCE) handler called upon
assertion of MCERR# will not have any way to determine the cause of the MCE.
• The Overflow Error bit (bit 62) in the IA32_MC0_STATUS register indicates, when set, that a
machine check error occurred while the results of a previous error were still in the error reporting
bank (i.e. The Valid bit was set when the new error occurred). If an uncorrectable error is logged in
the error-reporting bank and another error occurs, the overflow bit will not be set.
• The MCA Error Code field of the IA32_MC0_STATUS register gets written by a different
mechanism than the rest of the register. For uncorrectable errors, the other fields in the
IA32_MC0_STATUS register are only updated by the first error. Any further errors that are detected