Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology* on 90 nm Process Technology Specification Update

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Specification Update 25
Q28.
Enabling No-Eviction Mode (NEM) May Prevent the Operation of the Second
Logical Processor in a Hyper-Threading Technology Enabled Processor
Problem: In an HT Technology enabled system, when NEM is enabled by setting Bit 0 of MSR 080h
(IA32_BIOS_CACHE_AS_RAM), the second logical processor may fail to wake up from "Wait-for-
SIPI" state.
Implication: In an HT Technology enabled system, the second logical processor may not respond to SIPI. The OS
will continue to operate but only with a single logical processor.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
Q29.
Interactions Between the Instruction Translation Lookaside Buffer (ITLB) and
the Instruction Streaming Buffer May Cause Unpredictable Software Behavior
Problem: Complex interactions within the instruction fetch / decode unit may make it possible for the processor to
execute instructions from an internal streaming buffer containing stale or incorrect information.
Implication: When this erratum occurs, an incorrect instruction stream may be executed resulting in unpredictable
software behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
Q30.
STPCLK# Signal Assertion under Certain Conditions May Cause a System Hang
Problem: The assertion of STPCLK# signal before a logical processor awakens from the "Wait-for-SIPI" state for
the first time, may cause a system hang. A processor supporting Hyper-Threading Technology may fail
to initialize appropriately, and may not issue a Stop Grant Acknowledge special bus cycle in response to
the second STPCLK# assertion.
Implication: When this erratum occurs in an HT Technology enabled system, it may cause a system hang.
Workaround: BIOS should initialize the second thread of the processor supporting Hyper-Threading Technology prior
to STPCLK# assertion. Additionally, it is possible for the BIOS to contain a workaround for this
erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
Q31.
Sequence of Locked Operations Can Cause Two Threads to Receive Stale Data
and Cause Application Hang
Problem: While going through a sequence of locked operations, it is possible for the two threads to receive stale
data. This is a violation of expected memory ordering rules and the application may hang.
Implication: When this erratum occurs in an HT Technology-enabled system, the application may hang.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.