Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology* on 90 nm Process Technology Specification Update

R
24 Specification Update
Q25.
xAPIC May Not Report Some Illegal Vector Errors
Problem: The local xAPIC has an Error Status Register, which records all errors. The bit 6 (the Receive Illegal
Vector bit) of this register, is set when the local xAPIC detects an illegal vector in a received message.
When an illegal vector error is received on the same internal clock that the error status register is being
written (due to a previous error), bit 6 does not get set and illegal vector errors are not flagged.
Implication: The xAPIC may not report some Illegal Vector errors when they occur at approximately the same time
as other xAPIC errors. The other xAPIC errors will continue to be reported.
Workaround: None Identified
Status: For the steppings affected, see the Summary Tables of Changes.
Q26.
Incorrect Duty Cycle is Chosen when On-Demand Clock Modulation is Enabled
in a Processor Supporting Hyper-Threading Technology
Problem: When a processor supporting Hyper-Threading Technology (HT Technology) enables On-Demand
Clock Modulation on both logical processors, the processor is expected to select the lowest duty cycle of
the two potentially different values. When one logical processor enters the AUTOHALT state, the duty
cycle implemented should be unaffected by the halted logical processor. Due to this erratum, the duty
cycle is incorrectly chosen to be the higher duty cycle of both logical processors.
Implication: Due to this erratum, higher duty cycle may be chosen when the On-Demand Clock Modulation is
enabled on both logical processors.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
Q27.
Memory Aliasing of Pages As Uncacheable Memory Type and Write Back (WB)
May Hang the System
Problem: When a page is being accessed as either Uncacheable (UC) or Write Combining (WC) and WB, under
certain bus and memory timing conditions, the system may loop in a continual sequence of UC fetch,
implicit writeback, and Request For Ownership (RFO) retries.
Implication: This erratum has not been observed in any commercially available operating system or application. The
aliasing of memory regions, a condition necessary for this erratum to occur, is documented as being
unsupported in the
IA-32 Intel® Architecture Software Developer's Manual, Volume 3, section 10.12.4,
Programming the PAT. However, if this erratum occurs the system may hang.
Workaround: The pages should not be mapped as either UC or WC and WB at the same time.
Status: For the steppings affected, see the Summary Tables of Changes.