Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology* on 90 nm Process Technology Specification Update

R
Specification Update 23
Q22.
Some Front Side Bus I/O Specifications Are Not Met
Problem: The following front side bus I/O specifications are not met:
• The VIH(min) for the GTL+ signals is specified as GTLREF + (0.10 * VCC) [V].
• The VIH(min) for the Asynchronous GTL+ signals is specified as Vcc/2 + (0.10 * VCC) [V].
• Common Clock Output Valid Delay(min) is specified as -0.250 ns.
• Common Clock Input Setup Time is specified as 0.700 ns.
• Source Synchronous Input Setup Time to Strobe is specified as 0.150 ns.
• Source Synchronous Input Hold Time to Strobe is specified as 0.150 ns.
Implication: This erratum can cause functional failures depending upon system bus activity. It can manifest itself as
data parity, address parity, and/or machine check errors.
Workaround: Due to this erratum, the system should meet the following voltage levels and processor timings:
• The V
IH(min)
for GTL+ signals is now GTLREF + (0.20 * V
CC
) [V].
• The V
IH(min)
for the Asynchronous GTL+ signals is now Vcc/2 + (0.20 * V
CC
) [V].
• Common Clock Output Valid Delay(min) is now -0.300 ns.
• Common Clock Input Setup Time is now 0.900 ns.
• Source Synchronous Input Setup Time to Strobe is now 0.350 ns.
• Source Synchronous Input Hold Time to Strobe is now 0.350 ns.
Status: For the steppings affected, see the Summary Tables of Changes.
Q23.
Incorrect Physical Address Size Returned by CPUID Instruction
Problem: The CPUID instruction Function 80000008H (Extended Address Sizes Function) returns the address
sizes supported by the processor in the EAX register. This Function returns an incorrect physical address
size value of 40 bits. The correct physical address size is 36 bits.
Implication: Function 80000008H returns an incorrect physical address size value of 40 bits.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
Q24.
Incorrect Debug Exception (#DB) May Occur When a Data Breakpoint Is Set on
an FP Instruction
Problem: The default Microcode Floating Point Event Handler routine executes a series of loads to obtain data
about the FP instruction that is causing the FP event. If a data breakpoint is set on the instruction causing
the FP event, the load in the microcode routine will trigger the data breakpoint resulting in a debug
exception.
Implication: An incorrect Debug Exception (#DB) may occur if data breakpoint is placed on an FP instruction. Intel
has not observed this erratum with any commercially available software or system.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.