Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology* on 90 nm Process Technology Specification Update

22 Specification Update

Q19.

Parity Error in the L1 Cache May Cause the Processor to Hang

Problem: If a locked operation accesses a line in the L1 cache that has a parity error, it is possible that the

processor may hang while trying to evict the line.

Implication: If this erratum occurs, it may result in a system hang. Intel has not observed this erratum with any

commercially available software.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

Q20.

A 16-bit Address Wrap Resulting from a Near Branch (Jump or Call) May Cause

an Incorrect Address to Be Reported to the #GP Exception Handler

Problem: If a 16-bit application executes a branch instruction that causes an address wrap to a target address

outside of the code segment, the address of the branch instruction should be provided to the general

protection exception handler. It is possible that, as a result of this erratum, that the general protection

handler may be called with the address of the branch target.

Implication: The 16-bit software environment which is affected by this erratum, will see that the address reported by

the exception handler points to the target of the branch, rather than the address of the branch instruction.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

Q21.

Locks and SMC Detection May Cause the Processor to Temporarily Hang

Problem: The processor may temporarily hang in a Hyper-Threading Technology (HT Technology) enabled

system if one logical processor executes a synchronization loop that includes one or more locks and is

waiting for release by the other logical processor. If the releasing logical processor is executing

instructions that are within the detection range of the self modifying code (SMC) logic, then the

processor may be locked in the synchronization loop until the arrival of an interrupt or other event.

Implication: If this erratum occurs in a Hyper-Threading Technology (HT Technology) enabled system, the

application may temporarily stop making forward progress. Intel has not observed this erratum with any

commercially available software.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.