Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology* on 90 nm Process Technology Specification Update

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Specification Update 21
Q16.
System May Hang if a Fatal Cache Error Causes Bus Write Line (BWL)
Transaction to Occur to the Same Cache Line Address as an Outstanding Bus
Read Line (BRL) or Bus Read-Invalidate Line (BRIL)
Problem: A processor internal cache fatal data ECC error may cause the processor to issue a BWL transaction to
the same cache line address as an outstanding BRL or BRIL. As it is not typical behavior for a single
processor to have a BWL and a BRL/BRIL concurrently outstanding to the same address, this may
represent an unexpected scenario to system logic within the chipset.
Implication: The processor may not be able to fully execute the machine check handler in response to the fatal cache
error if system logic does not ensure forward progress on the System Bus under this scenario.
Workaround: System logic should ensure completion of the outstanding transactions. Note that during recovery from
a fatal data ECC error, memory image coherency of the BWL with respect to BRL/BRIL transactions is
not important. Forward progress is the primary requirement.
Status: For the steppings affected, see the Summary Tables of Changes.
Q17.
A Write to APIC Task Priority Register (TPR) that Lowers Priority May Seem to
Have Not Occurred
Problem: Uncacheable stores to the APIC space are handled in a non-synchronous way with respect to the speed at
which instructions are retired. If an instruction that masks the interrupt flag e.g. CLI is executed soon
after an uncacheable write to the TPR that lowers the APIC priority the interrupt masking operation may
take effect before the actual priority has been lowered. This may cause interrupts whose priority is lower
than the initial TPR but higher than the final TPR to not be serviced until the interrupt flag is finally
cleared e.g. STI. Interrupts will remain pended and are not lost
Implication: This condition may allow interrupts to be accepted by the processor but may delay their service.
Workaround: This can be avoided by issuing a TPR Read after a TPR Write that lowers the TPR value. This will force
the store to the APIC priority resolution logic before any subsequent instructions are executed. No
commercial operating system is known to be impacted by this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
Q18.
ITP Cannot Continue Single Step Execution after the First Breakpoint
Problem: ITP will not continue in single step execution after the first software breakpoint. ITP is unable to reset
the Resume Flag (RF) bit in the EFLAGS Register.
Implication: The processor repeatedly breaks at the instruction breakpoint address instead of single stepping.
Workaround: Execution after the break will continue if DR7 bit 1 (Global Breakpoint Enable) is manually cleared.
Status: For the steppings affected, see the Summary Tables of Changes.