Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology* on 90 nm Process Technology Specification Update

R
10 Specification Update
NO. D0 E0 Plans ERRATA
Q40 X X NoFix
Data Breakpoints on the High Half of a Floating Point Line Split may not be
Captured
Q41 X X NoFix
Machine Check Exceptions May not Update Last-Exception Record MSRs
(LERs)
Q42 X X NoFix MOV CR3 Performs Incorrect Reserved Bit Checking When in PAE Paging
Q43 X X NoFix
Stores to Page Tables May Not Be Visible to Pagewalks for Subsequent Loads
Without Serializing or Invalidating the Page Table Entry
Q44 X PlanFix A Split Store Memory Access May Miss a Data Breakpoint
Q45 X X PlanFix
Execution of IRET or INTn Instructions May Cause Unexpected System
Behavior
Q46 X X NoFix
Checking of Page Table Base Address May Not Match the Address Bit Width
Supported by the Platform
Q47 X X NoFix
The IA32_MCi_STATUS MSR May Improperly Indicate that Additional MCA
Information Has Been Captured
Q48 X X NoFix
With TF (Trap Flag) Asserted, FP Instruction That Triggers an Unmasked FP
Exception May Take Single Step Trap Before Retirement of Instruction
Q49 X Fixed
MCA Corrected Memory Hierarchy Error Counter May Not Increment
Correctly
Q50 X X NoFix
BTS(Branch Trace Store) and PEBS(Precise Event Based Sampling) May
Update Memory outside the BTS/PEBS Buffer
Q51 X PlanFix Processor May Hang When Resuming from Deep Sleep State
Q52 X X No Fix
Memory Ordering Failure May Occur with Snoop Filtering Third Party Agents
after Issuing and Completing a BWIL (Bus Write Invalidate Line) or BLW (Bus
Locked Write) Transaction
Q53 X X No Fix
Control Register 2 (CR2) Can be Updated during a REP MOVS/STOS
Instruction with Fast Strings Enabled
Q54 X X PlanFix
TPR (Task Priority Register) Updates during Voltage Transitions of Power
Management Events May Cause a System Hang
Q55 X X PlanFix
Running in SMM (System Management Mode) and L1 Data Cache Adaptive
Mode May Cause Unexpected System Behavior when SMRAM is Mapped to
Cacheable Memory
Q56 X X No Fix
Voltage and Frequency Transition May Not Occur if a Voltage Transition is
Interrupted by a Warm Reset
Q57 X X Plan Fix
It Is Possible That Two Specific Invalid Opcodes May Cause Unexpected
Memory Accesses
Q58 X X No Fix
At Core-to-Bus Ratios of 16:1 and above Defer Reply Transactions with Non-
Zero REQb Values May Cause a Front Side Bus Stall
Q59 X X No Fix
The Processor May Issue Front Side Bus Transactions up to 6 Clocks after
RESET# is Asserted
Q60 X X No Fix
Front Side Bus Machine Checks May be Reported as a Result of On-Going
Transactions during Warm Reset
Q61 X X No Fix
Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause
an Unexpected Interrupt
Q62 X X No Fix
The Processor May Issue Multiple Code Fetches to the Same Cache Line for
Systems with Slow Memory