Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

B-42 Vol. 2B

INSTRUCTION FORMATS AND ENCODINGS

ROL – Rotate Left

byteregister by 1 0100 000B 1101 0000 : 11 000 bytereg

qwordregister by 1 0100 100B 1101 0001 : 11 000 qwordreg

memory by 1 0100 00XB 1101 000w : mod 000 r/m

memory8 by 1 0100 00XB 1101 0000 : mod 000 r/m

memory64 by 1 0100 10XB 1101 0001 : mod 000 r/m

byteregister by CL 0100 000B 1101 0010 : 11 000 bytereg

qwordregister by CL 0100 100B 1101 0011 : 11 000 qwordreg

memory by CL 0100 00XB 1101 001w : mod 000 r/m

memory8 by CL 0100 00XB 1101 0010 : mod 000 r/m

memory64 by CL 0100 10XB 1101 0011 : mod 000 r/m

byteregister by immediate count 0100 000B 1100 0000 : 11 000 bytereg :

imm8

qwordregister by immediate count 0100 100B 1100 0001 : 11 000 bytereg :

imm8

memory by immediate count 1100 000w : mod 000 r/m : imm8

memory8 by immediate count 0100 00XB 1100 0000 : mod 000 r/m : imm8

memory64 by immediate count 0100 10XB 1100 0001 : mod 000 r/m : imm8

ROR – Rotate Right

byteregister by 1 0100 000B 1101 0000 : 11 001 bytereg

qwordregister by 1 0100 100B 1101 0001 : 11 001 qwordreg

memory by 1 0100 00XB 1101 000w : mod 001 r/m

memory8 by 1 0100 00XB 1101 0000 : mod 001 r/m

memory64 by 1 0100 10XB 1101 0001 : mod 001 r/m

byteregister by CL 0100 000B 1101 0010 : 11 001 bytereg

Table B-15. General Purpose Instruction Formats and Encodings

for 64-Bit Mode (Contd.)

Instruction and Format Encoding