Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B 4-37
INSTRUCTION SET REFERENCE, N-Z
PADDQ—Add Packed Quadword Integers
Description
Adds the first operand (destination operand) to the second operand (source operand)
and stores the result in the destination operand. The source operand can be a quad-
word integer stored in an MMX technology register or a 64-bit memory location, or it
can be two packed quadword integers stored in an XMM register or an 128-bit
memory location. The destination operand can be a quadword integer stored in an
MMX technology register or two packed quadword integers stored in an XMM register.
When packed quadword operands are used, a SIMD add is performed. When a quad-
word result is too large to be represented in 64 bits (overflow), the result is wrapped
around and the low 64 bits are written to the destination element (that is, the carry
is ignored).
Note that the PADDQ instruction can operate on either unsigned or signed (two’s
complement notation) integers; however, it does not set bits in the EFLAGS register
to indicate overflow and/or a carry. To prevent undetected overflow conditions, soft-
ware must control the ranges of the values operated on.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Operation
PADDQ instruction with 64-Bit operands:
DEST[63:0] ← DEST[63:0] + SRC[63:0];
PADDQ instruction with 128-Bit operands:
DEST[63:0] ← DEST[63:0] + SRC[63:0];
DEST[127:64] ← DEST[127:64] + SRC[127:64];
Intel C/C++ Compiler Intrinsic Equivalents
PADDQ __m64 _mm_add_si64 (__m64 a, __m64 b)
PADDQ __m128i _mm_add_epi64 ( __m128i a, __m128i b)
Opcode Instruction
64-Bit
Mode
Compat/
Leg Mode Description
0F D4 /r PADDQ mm1,
mm2/m64
Valid Valid Add quadword integer
mm2/m64 to mm1.
66 0F D4 /r PADDQ xmm1,
xmm2/m128
Valid Valid Add packed quadword
integers xmm2/m128 to
xmm1.