Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B 4-171
INSTRUCTION SET REFERENCE, N-Z
The destination operand may be an MMX technology register or an XMM register; the
count operand can be either an MMX technology register or an 64-bit memory loca-
tion, an XMM register or a 128-bit memory location, or an 8-bit immediate. Note that
only the first 64-bits of a 128-bit count operand are checked to compute the count.
The PSLLW instruction shifts each of the words in the destination operand to the left
by the number of bits specified in the count operand; the PSLLD instruction shifts
each of the doublewords in the destination operand; and the PSLLQ instruction shifts
the quadword (or quadwords) in the destination operand.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Operation
PSLLW instruction with 64-bit operand:
IF (COUNT > 15)
THEN
DEST[64:0] ← 0000000000000000H;
ELSE
DEST[15:0] ← ZeroExtend(DEST[15:0]
<< COUNT);
(* Repeat shift operation for 2nd and 3rd words *)
DEST[63:48] ← ZeroExtend(DEST[63:48]
<< COUNT);
FI;
PSLLD instruction with 64-bit operand:
IF (COUNT > 31)
THEN
DEST[64:0] ← 0000000000000000H;
ELSE
DEST[31:0] ← ZeroExtend(DEST[31:0]
<< COUNT);
DEST[63:32] ← ZeroExtend(DEST[63:32]
<< COUNT);
FI;
PSLLQ instruction with 64-bit operand:
IF (COUNT > 63)
Figure 4-8. PSLLW, PSLLD, and PSLLQ Instruction Operation Using 64-bit Operand
DEST
DEST
Pre-Shift
Post-Shift
Shift Left
X0
X0
<< COUNT
X3 X2 X1
X1 << COUNTX2 << COUNTX3 << COUNT
with Zero
Extension