Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-168 Vol. 2B
INSTRUCTION SET REFERENCE, N-Z
PSLLDQ—Shift Double Quadword Left Logical
Description
Shifts the destination operand (first operand) to the left by the number of bytes spec-
ified in the count operand (second operand). The empty low-order bytes are cleared
(set to all 0s). If the value specified by the count operand is greater than 15, the
destination operand is set to all 0s. The destination operand is an XMM register. The
count operand is an 8-bit immediate.
Operation
TEMP ← COUNT;
IF (TEMP
> 15) THEN TEMP ← 16; FI;
DEST ← DEST
<< (TEMP ∗ 8);
Intel C/C++ Compiler Intrinsic Equivalent
PSLLDQ __m128i _mm_slli_si128 ( __m128i a, int imm)
Flags Affected
None.
Numeric Exceptions
None.
Protected Mode Exceptions
#UD If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
If CPUID.01H:EDX.SSE2[bit 26] = 0.
#NM If CR0.TS[bit 3] = 1.
Real-Address Mode Exceptions
Same exceptions as in Protected Mode.
Opcode Instruction
64-Bit
Mode
Compat/
Leg
Mode Description
66 0F 73 /7 ib PSLLDQ xmm1,
imm8
Valid Valid Shift xmm1 left by imm8 bytes
while shifting in 0s.