Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B 4-73
INSTRUCTION SET REFERENCE, N-Z
PHADDW/PHADDD — Packed Horizontal Add
Description
PHADDW adds two adjacent 16-bit signed integers horizontally from the source and
destination operands and packs the 16-bit signed results to the destination operand
(first operand). PHADDD adds two adjacent 32-bit signed integers horizontally from
the source and destination operands and packs the 32-bit signed results to the desti-
nation operand (first operand). Both operands can be MMX or XMM registers. When
the source operand is a 128-bit memory operand, the operand must be aligned on a
16-byte boundary or a general-protection exception (#GP) will be generated.
In 64-bit mode, use the REX prefix to access additional registers.
Operation
PHADDW with 64-bit operands:
mm1[15-0] = mm1[31-16] + mm1[15-0];
mm1[31-16] = mm1[63-48] + mm1[47-32];
mm1[47-32] = mm2/m64[31-16] + mm2/m64[15-0];
mm1[63-48] = mm2/m64[63-48] + mm2/m64[47-32];
PHADDW with 128-bit operands :
xmm1[15-0] = xmm1[31-16] + xmm1[15-0];
xmm1[31-16] = xmm1[63-48] + xmm1[47-32];
xmm1[47-32] = xmm1[95-80] + xmm1[79-64];
xmm1[63-48] = xmm1[127-112] + xmm1[111-96];
xmm1[79-64] = xmm2/m128[31-16] + xmm2/m128[15-0];
xmm1[95-80] = xmm2/m128[63-48] + xmm2/m128[47-32];
xmm1[111-96] = xmm2/m128[95-80] + xmm2/m128[79-64];
xmm1[127-112] = xmm2/m128[127-112] + xmm2/m128[111-96];
Opcode Instruction
64-Bit
Mode
Compat/
Leg Mode
Description
0F 38 01 /r PHADDW mm1,
mm2/m64
Valid Valid Add 16-bit signed integers
horizontally, pack to MM1.
66 0F 38 01 /r PHADDW xmm1,
xmm2/m128
Valid Valid Add 16-bit signed integers
horizontally, pack to XMM1.
0F 38 02 /r PHADDD mm1,
mm2/m64
Valid Valid Add 32-bit signed integers
horizontally, pack to MM1.
66 0F 38 02 /r PHADDD xmm1,
xmm2/m128
Valid Valid Add 32-bit signed integers
horizontally, pack to XMM1.