Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

B-20 Vol. 2B
INSTRUCTION FORMATS AND ENCODINGS
SAR – Shift Arithmetic Right
register by 1 1101 000w : 11 111 reg
memory by 1 1101 000w : mod 111 r/m
register by CL 1101 001w : 11 111 reg
memory by CL 1101 001w : mod 111 r/m
register by immediate count 1100 000w : 11 111 reg : imm8 data
memory by immediate count 1100 000w : mod 111 r/m : imm8 data
SBB – Integer Subtraction with Borrow
register1 to register2 0001 100w : 11 reg1 reg2
register2 to register1 0001 101w : 11 reg1 reg2
memory to register 0001 101w : mod reg r/m
register to memory 0001 100w : mod reg r/m
immediate to register 1000 00sw : 11 011 reg : immediate data
immediate to AL, AX, or EAX 0001 110w : immediate data
immediate to memory 1000 00sw : mod 011 r/m : immediate data
SCAS/SCASB/SCASW/SCASD – Scan String 1010 111w
SETcc – Byte Set on Condition
register 0000 1111 : 1001 tttn : 11 000 reg
memory 0000 1111 : 1001 tttn : mod 000 r/m
SGDT – Store Global Descriptor Table Register 0000 1111 : 0000 0001 : mod
A
000 r/m
SHL – Shift Left
register by 1 1101 000w : 11 100 reg
memory by 1 1101 000w : mod 100 r/m
register by CL 1101 001w : 11 100 reg
memory by CL 1101 001w : mod 100 r/m
register by immediate count 1100 000w : 11 100 reg : imm8 data
memory by immediate count 1100 000w : mod 100 r/m : imm8 data
SHLD – Double Precision Shift Left
register by immediate count 0000 1111 : 1010 0100 : 11 reg2 reg1 : imm8
memory by immediate count 0000 1111 : 1010 0100 : mod reg r/m : imm8
Table B-13. General Purpose Instruction Formats and Encodings
for Non-64-Bit Modes (Contd.)
Instruction and Format Encoding