Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

Vol. 2B 4-231
INSTRUCTION SET REFERENCE, N-Z
tempCF ← MSB(DEST);
DEST ← (DEST
∗ 2) + tempCF;
tempCOUNT ← tempCOUNT – 1;
OD;
ELIHW;
CF ← LSB(DEST);
IF COUNT
= 1
THEN OF ← MSB(DEST) XOR CF;
ELSE OF is undefined;
FI;
FI;
(* ROR instruction operation *)
IF tempCOUNT > 0) (* Prevent updates to CF *)
WHILE (tempCOUNT
≠ 0)
DO
tempCF ← LSB(SRC);
DEST ← (DEST / 2) + (tempCF
∗ 2
SIZE
);
tempCOUNT ← tempCOUNT – 1;
OD;
ELIHW;
CF ← MSB(DEST);
IF COUNT
= 1
THEN OF ← MSB(DEST) XOR MSB − 1(DEST);
ELSE OF is undefined;
FI;
FI;
Flags Affected
The CF flag contains the value of the bit shifted into it. The OF flag is affected only for
single-bit rotates (see “Description” above); it is undefined for multi-bit rotates. The
SF, ZF, AF, and PF flags are not affected.
Protected Mode Exceptions
#GP(0) If the source operand is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS,
ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment
selector.
#SS(0) If a memory operand effective address is outside the SS
segment limit.
#PF(fault-code) If a page fault occurs.