Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-120 Vol. 2B
INSTRUCTION SET REFERENCE, N-Z
PMULLW—Multiply Packed Signed Integers and Store Low Result
Description
Performs a SIMD signed multiply of the packed signed word integers in the destina-
tion operand (first operand) and the source operand (second operand), and stores
the low 16 bits of each intermediate 32-bit result in the destination operand.
(Figure 4-3 shows this operation when using 64-bit operands.) The source operand
can be an MMX technology register or a 64-bit memory location, or it can be an XMM
register or a 128-bit memory location. The destination operand can be an MMX tech-
nology register or an XMM register.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Operation
PMULLW instruction with 64-bit operands:
TEMP0[31:0] ← DEST[15:0]
∗ SRC[15:0]; (* Signed multiplication *)
TEMP1[31:0] ← DEST[31:16]
∗ SRC[31:16];
TEMP2[31:0] ← DEST[47:32]
∗ SRC[47:32];
TEMP3[31:0] ← DEST[63:48]
∗ SRC[63:48];
Opcode Instruction
64-Bit
Mode
Compat/
Leg Mode Description
0F D5 /r PMULLW mm,
mm/m64
Valid Valid Multiply the packed signed word
integers in mm1 register and
mm2/m64, and store the low 16
bits of the results in mm1.
66 0F D5 /r PMULLW xmm1,
xmm2/m128
Valid Valid Multiply the packed signed word
integers in xmm1 and
xmm2/m128, and store the low
16 bits of the results in xmm1.
Figure 4-4. PMULLU Instruction Operation Using 64-bit Operands
X3 X2 X1 X0
Z3 = X3 ∗ Y3 Z2 = X2 ∗ Y2 Z1 = X1 ∗ Y1 Z0 = X0 ∗ Y0
SRC
DEST
DEST
Y3 Y2 Y1 Y0
TEMP
Z3[15:0] Z2[15:0] Z1[15:0] Z0[15:0]