Intel 64 and IA-32 Architectures Software Developers Manual Volume 2B, Instruction Set Reference, N-Z

4-86 Vol. 2B
INSTRUCTION SET REFERENCE, N-Z
DEST ← (DEST AND NOT MASK) OR (((SRC << (SEL ∗ 16)) AND MASK);
PINSRW instruction with 128-bit source operand:
SEL ← COUNT AND 7H;
CASE (Determine word position) OF
SEL ← 0: MASK ← 0000000000000000000000000000FFFFH;
SEL ← 1: MASK ← 000000000000000000000000FFFF0000H;
SEL ← 2: MASK ← 00000000000000000000FFFF00000000H;
SEL ← 3: MASK ← 0000000000000000FFFF000000000000H;
SEL ← 4: MASK ← 000000000000FFFF0000000000000000H;
SEL ← 5: MASK ← 00000000FFFF00000000000000000000H;
SEL ← 6: MASK ← 0000FFFF000000000000000000000000H;
SEL ← 7: MASK ← FFFF0000000000000000000000000000H;
DEST ← (DEST AND NOT MASK) OR (((SRC << (SEL ∗ 16)) AND MASK);
Intel C/C++ Compiler Intrinsic Equivalent
PINSRW __m64 _mm_insert_pi16 (__m64 a, int d, int n)
PINSRW __m128i _mm_insert_epi16 ( __m128i a, int b, int imm)
Flags Affected
None.
Numeric Exceptions
None.
Protected Mode Exceptions
#GP(0) If a memory operand effective address is outside the CS, DS,
ES, FS, or GS segment limit.
#SS(0) If a memory operand effective address is outside the SS
segment limit.
#UD If CR0.EM[bit 2] = 1.
(128-bit operations only) If CR4.OSFXSR[bit 9] = 0.
(128-bit operations only) If CPUID.01H:EDX.SSE2[bit 26] = 0.
#NM If CR0.TS[bit 3] = 1.
#MF (64-bit operations only) If there is a pending x87 FPU exception.
#PF(fault-code) If a page fault occurs.
#AC(0) (64-bit operations only) If alignment checking is enabled and an
unaligned memory reference is made while the current privilege
level is 3.