Mobile Intel Pentium 4 Processor with 533 MHz System Bus Specification Update

R
8 Specification Update
M = Mobile Intel
®
Celeron
®
processor
N = Intel
®
Pentium
®
4 processor
O = Intel
®
Xeon
®
processor MP
P = Intel
®
Xeon
®
processor
Q = Mobile Intel
®
Pentium
®
4 processor supporting Hyper-Threading Technology on 90-nm technology
process
R = Intel
®
Pentium
®
4 processor on 90 nm process
S = Intel
®
Xeon
®
Processor with 800 MHz System Bus
T = Mobile Intel
®
Pentium
®
4 processor – M
V = Intel
®
Celeron
®
processor in the 478-Pin Package
W = Intel
®
Celeron
®
M processor
X = Intel
®
Pentium
®
M processor on 90 nm process with 2-MB L2 cache
Y = Intel
®
Pentium
®
M processor
Z = Mobile Intel
®
Pentium
®
4 processor with 533 MHz System Bus
Stepping
NO.
D1
Plans ERRATA
Z1 X NoFix I/O restart in SMM may fail after simultaneous machine check exception (MCE)
Z2 X NoFix
MCA registers may contain invalid information if RESET# occurs and PWRGOOD
is not held asserted
Z3 X NoFix Transaction is not retried after BINIT#
Z4 X NoFix Invalid opcode 0FFFh requires a ModRM byte
Z5 X NoFix
FSW may not be completely restored after page fault on FRSTOR or FLDENV
instructions
Z6 X NoFix The processor flags #PF instead of #AC on an unlocked CMPXCHG8B instruction
Z7 X NoFix
When in no-fill mode the memory type of large pages are incorrectly forced to
uncacheable
Z8 X NoFix
Processor may hang due to speculative page walks to non-existent system
memory
Z9 NoFix
MCA error code field in IA32_MC0_STATUS register may become out of sync with
the rest of the register
Z10 X NoFix
The IA32_MC1_STATUS register may contain incorrect information for correctable
errors
Z11 X NoFix Debug mechanisms may not function as expected
Z12 X NoFix Machine check architecture error reporting and recovery may not work as expected
Z13 X NoFix
Cascading of performance counters does not work correctly when forced overflow
is enabled
Z14 X NoFix EMON event counting of x87 loads may not work as expected
Z15 PlanFix Buffer on resistance may exceed specification
Z16 X NoFix Processor issues inconsistent transaction size attributes for locked operation
Z17 X NoFix
When the processor is in the System Management Mode (SMM), debug registers
may be fully writeable