Mobile Intel Pentium 4 Processor with 533 MHz System Bus Specification Update

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Specification Update 25
Z30.
System Bus Interrupt Messages without Data that Receive a HardFailure
Response May Hang the Processor
Problem: When a system bus agent (processor or chipset) issues an interrupt transaction without data onto the
system bus and the transaction receives a HardFailure response, a potential processor hang can occur.
The processor, which generates an inter-processor interrupt (IPI) that receives the HardFailure response,
will still log the MCA error event cause as HardFailure, even if the APIC causes a hang. Other
processors, which are true targets of the IPI, will also hang on hardfail-without-data, but will not record
an MCA HardFailure event as the cause. If a HardFailure response occurs on a system bus interrupt
message with data, the APIC will complete the operation so as not to hang the processor.
Implication: The processor may hang.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
Z31.
Memory Type of the Load Lock Different from its Corresponding Store Unlock
Problem: A use-once protocol is employed to ensure that the processor in a multi-agent system may access data
that is loaded into its cache on a Read-for-Ownership operation at least once before it is snooped out by
another agent. This protocol is necessary to avoid a multi-agent livelock scenario in which the processor
cannot gain ownership of a line and modify it before that data is snooped out by another agent. In the
case of this erratum, split load lock instructions incorrectly trigger the use-once protocol. A load lock
operation accesses data that splits across a page boundary with both pages of WB memory type. The
use-once protocol activates and the memory type for the split halves get forced to UC. Since use-once
does not apply to stores, the store unlock instructions go out as WB memory type. The full sequence on
the bus is: locked partial read (UC), partial read (UC), partial write (WB), locked partial write (WB).
The use-once protocol should not be applied to load locks.
Implication: When this erratum occurs, the memory type of the load lock will be different than the memory type of
the store unlock operation. This behavior (load locks and store unlocks having different memory types)
does not introduce any functional failures such as system hangs or memory corruption.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
Z32.
Shutdown and IERR# May Result Due to a Machine Check Exception on a Hyper-
Threading Technology Enabled Processor
Problem: When a Machine Check Exception (MCE) occurs due to an internal error, both logical processors on a
Hyper-Threading Technology enabled processor normally vector to the MCE handler. However, if one
of the logical processors is in the “Wait-for-SIPI” state, that logical processor will not have an MCE
handler and will shut down and assert IERR#.
Implication: A processor with a logical processor in the “Wait-for-SIPI” state will shut down when an MCE occurs
on the other thread.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.