Mobile Intel Pentium 4 Processor with 533 MHz System Bus Specification Update

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Specification Update 21
Z19.
Processor May Hang under Certain Frequencies and 12.5% STPCLK# Duty Cycle
Problem: If a system de-asserts STPCLK# at a 12.5% duty cycle, the processor is running below 2 GHz, and the
processor thermal control circuit (TCC) on-demand clock modulation is active, the processor may hang.
This erratum does not occur under the automatic mode of the TCC.
Implication: When this erratum occurs, the processor will hang.
Workaround: If use of the on-demand mode of the processor's TCC is desired in conjunction with STPCLK#
modulation, then assure that STPCLK# is not asserted at a 12.5% duty cycle.
Status: For the steppings affected, see the Summary Tables of Changes.
Z20.
System May Hang if a Fatal Cache Error Causes Bus Write Line (BWL)
Transaction to Occur to the Same Cache Line Address as an Outstanding Bus
Read Line (BRL) or Bus Read-Invalidate Line (BRIL)
Problem: A processor internal cache fatal data ECC error may cause the processor to issue a BWL transaction to
the same cache line address as an outstanding BRL or BRIL. As it is not typical behavior for a single
processor to have a BWL and a BRL/BRIL concurrently outstanding to the same address, this may
represent an unexpected scenario to system logic within the chipset.
Implication: The processor may not be able to fully execute the machine check handler in response to the fatal cache
error if system logic does not ensure forward progress on the system bus under this scenario.
Workaround: System logic should ensure completion of the outstanding transactions. Note that during recovery from a
fatal data ECC error, memory image coherency of the BWL with respect to BRL/BRIL transactions is
not important. Forward progress is the primary requirement.
Status: For the steppings affected, see the Summary Tables of Changes.
Z21.
Simultaneous Assertion of A20M# and INIT# May Result in Incorrect Data Fetch
Problem: If A20M# and INIT# are simultaneously asserted by software, followed by a data access to the
0xFFFFFXXX memory region, with A20M# still asserted, incorrect data will be accessed. With A20M#
asserted, an access to 0xFFFFFXXX should result in a load from physical address 0xFFEFFXXX.
However, in the case of A20M# and INIT# being asserted together, the data load will actually be from
the physical address 0xFFFFFXXX. Code accesses are not affected by this erratum.
Implication: Processor may fetch incorrect data, resulting in BIOS failure.
Workaround: Deasserting and reasserting A20M# prior to the data access will workaround this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.