Mobile Intel Pentium 4 Processor with 533 MHz System Bus Specification Update

R
20 Specification Update
Z16.
Processor Issues Inconsistent Transaction Size Attributes for Locked Operation
Problem: When the processor is in the Page Address Extension (PAE) mode and detects the need to set the Access
and/or Dirty bits in the page directory or page table entries, the processor sends an 8 byte load lock onto
the system bus. A subsequent 8 byte store unlock is expected, but instead a 4 byte store unlock occurs.
Correct data is provided since only the lower bytes change, however external logic monitoring the data
transfer may be expecting an 8-byte store unlock.
Implication: No known commercially available chipsets are affected by this erratum.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
Z17.
When the Processor Is in the System Management Mode (SMM), Debug
Registers May Be Fully Writeable
Problem: When in System Management Mode (SMM), the processor executes code and stores data in the
SMRAM space. When the processor is in this mode and writes are made to DR6 and DR7, the processor
should block writes to the reserved bit locations. Due to this erratum, the processor may not block these
writes. This may result in invalid data in the reserved bit locations.
Implication: Reserved bit locations within DR6 and DR7 may become invalid.
Workaround: Software may perform a read/modify/write when writing to DR6 and DR7 to ensure that the values in
the reserved bits are maintained.
For the steppings affected, see the Summary Tables of Changes.
Z18.
IA32_MC0_ADDR and IA32_MC0_MISC Registers Will Contain Invalid or Stale
Data Following a Data, Address, or Response Parity Error
Problem: If the processor experiences a data, address, or response parity error, the ADDRV and MISCV bits of
the IA32_MC0_STATUS register are set, but the IA32_MC0_ADDR and IA32_MC0_MISC registers
are not loaded with data regarding the error.
Implication: When this erratum occurs, the IA32_MC0_ADDR and IA32_MC0_MISC registers will contain invalid
or stale data.
Workaround: Ignore any information in the IA32_MC0_ADDR and IA32_MC0_MISC registers after a data, address
or response parity error.
Status: For the steppings affected, see the Summary Tables of Changes.