Mobile Intel Pentium 4 Processor with 533 MHz Front Side Bus

74 Mobile Intel
®
Pentium
®
4 Processor with 533 MHz System Bus Datasheet
Configuration and Low Power Features
While in the Sleep state, the processor is capable of entering an even lower power state, the Deep
Sleep state, by asserting the DPSLP# pin. (See Section 6.2.6.) Once in the Sleep or Deep Sleep
states, the SLP# pin must be de-asserted if another asynchronous FSB event needs to occur. The
SLP# pin has a minimum assertion of one BCLK period.
When the processor is in Sleep state, it will not respond to interrupts or snoop transactions.
6.2.6 Deep Sleep State
Deep Sleep state is a very low power state the processor can enter while maintaining context. Deep
Sleep state is entered by asserting the DPSLP# pin. The DPSLP# pin must be deasserted to re-enter
the Sleep state. A period of 30 microseconds (to allow for PLL stabilization) must occur before the
processor can be considered to be in the Sleep State. Once in the Sleep state, the SLP# pin can be
deasserted to re-enter the Stop-Grant state.
The clock may be stopped when the processor is in the Deep Sleep state in order to support the
ACPI S1 state. The clock may only be stopped after DPSLP# is asserted and must be restarted
before DPSLP# is deasserted. To provide maximum power conservation when stopping the clock
during Deep Sleep, hold the BLCK0 input at V
OL
and the BCLK1 input at V
OH
.
While in Deep Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions of signals are allowed on the FSB while the processor is in
Deep Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant
state will result in unpredictable behavior.
6.2.7 Deeper Sleep State
The Deeper Sleep state is the lowest state power the processor can enter. This state is functionally
identical to the Deep Sleep state but at a lower core voltage. The control signals to the voltage
regulator to initiate a transition to the Deeper Sleep state are provided on the platform. Please refer
the appropriate platform design guidelines listed in Table 1.
6.3 Enhanced Intel SpeedStep Technology
The mobile Intel Pentium 4 processor, when used in conjunction with the requisite Intel SpeedStep
technology applet or its equivalent, supports Enhanced Intel SpeedStep technology. Enhanced Intel
SpeedStep technology allows the processor to switch between two core frequencies automatically
based on CPU demand, without having to reset the processor or change the FSB frequency. The
processor has two bus ratios and voltages programmed into it instead of one and the GHI# signal
controls which bus ratio and voltage is used. After reset, the processor will start in the lower of its
two core frequencies, the Battery Optimized mode. An operating mode transition to the high core
frequency can be made by setting GHI# low, putting the processor into the Deep Sleep state,
regulating to the new VID output, and returning to the Normal state. This puts the processor into
the high core frequency, or Maximum Performance mode. Going through these steps with GHI# set
high, transitions the processor back to the low core frequency operating mode. The processor will
drive the VID[4:0] pins with the VID of the current operating mode and the system logic is
required to regulate the core voltage within specification for the driven VID.