Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology on 90-nm Process Technology

Pin Listing and Signal Descriptions
44 Mobile Intel® Pentium® 4 Processor supporting Hyper-Threading Technology on 90-nm process technology Datasheet
G21 VSS Power/Other
G22 D10# Source Synch Input/Output
G23 D18# Source Synch Input/Output
G24 VSS Power/Other
G25 DBI1# Source Synch Input/Output
G26 D25# Source Synch Input/Output
H1 VSS Power/Other
H2 DRDY# Common Clock Input/Output
H3 REQ4# Source Synch Input/Output
H4 VSS Power/Other
H5 DBSY# Common Clock Input/Output
H6 BR0# Common Clock Input/Output
H21 D11# Source Synch Input/Output
H22 D16# Source Synch Input/Output
H23 VSS Power/Other
H24 D26# Source Synch Input/Output
H25 D31# Source Synch Input/Output
H26 VSS Power/Other
J1 REQ0# Source Synch Input/Output
J2 VSS Power/Other
J3 REQ3# Source Synch Input/Output
J4 REQ2# Source Synch Input/Output
J5 VSS Power/Other
J6 TRDY# Common Clock Input
J21 D14# Source Synch Input/Output
J22 VSS Power/Other
J23 DSTBP1# Source Synch Input/Output
J24 D29# Source Synch Input/Output
J25 VSS Power/Other
J26 DP0# Common Clock Input/Output
K1 A6# Source Synch Input/Output
K2 A3# Source Synch Input/Output
K3 VSS Power/Other
K4 A4# Source Synch Input/Output
K5 REQ1# Source Synch Input/Output
K6 VSS Power/Other
K21 VSS Power/Other
K22 DSTBN1# Source Synch Input/Output
K23 D30# Source Synch Input/Output
K24 VSS Power/Other
Table 4-2. Numerical Pin Assignment
(Sheet 5 of 12)
Pin # Pin Name
Signal Buffer
Type
Direction
K25 DP1# Common Clock Input/Output
K26 DP2# Common Clock Input/Output
L1 VSS Power/Other
L2 A9# Source Synch Input/Output
L3 A7# Source Synch Input/Output
L4 VSS Power/Other
L5 ADSTB0# Source Synch Input/Output
L6 A5# Source Synch Input/Output
L21 D24# Source Synch Input/Output
L22 D28# Source Synch Input/Output
L23 VSS Power/Other
L24 COMP0 Power/Other Input
L25 DP3# Common Clock Input/Output
L26 VSS Power/Other
M1 A13# Source Synch Input/Output
M2 VSS Power/Other
M3 A10# Source Synch Input/Output
M4 A11# Source Synch Input/Output
M5 VSS Power/Other
M6 A8# Source Synch Input/Output
M21 D27# Source Synch Input/Output
M22 VSS Power/Other
M23 D32# Source Synch Input/Output
M24 D35# Source Synch Input/Output
M25 VSS Power/Other
M26 D37# Source Synch Input/Output
N1 A12# Source Synch Input/Output
N2 A14# Source Synch Input/Output
N3 VSS Power/Other
N4 A15# Source Synch Input/Output
N5 A16# Source Synch Input/Output
N6 VSS Power/Other
N21 VSS Power/Other
N22 D33# Source Synch Input/Output
N23 D36# Source Synch Input/Output
N24 VSS Power/Other
N25 D39# Source Synch Input/Output
N26 D38# Source Synch Input/Output
P1 COMP1 Power/Other Input
P2 VSS Power/Other
Table 4-2. Numerical Pin Assignment
(Sheet 6 of 12)
Pin # Pin Name
Signal Buffer
Type
Direction