Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology* on 90 nm Process Technology Specification Update

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Specification Update 9
NO. D0 E0 Plans ERRATA
Q14 X X NoFix
Shutdown and IERR# may result due to a Machine Check Exception on a
Hyper-Threading technology enabled processor
Q15 X X NoFix
Processor may hang under certain frequencies and 12.5% STPCLK# duty
cycle
Q16 X X NoFix
System may hang if a fatal cache error causes Bus Write Line (BWL)
transaction to occur to the same cache line address as an outstanding Bus
Read Line (BRL) or Bus Read-Invalidate Line (BRIL)
Q17 X X NoFix
A write to APIC Task Priority Register (TPR) that lowers priority may seem to
have not occurred
Q18 X X NoFix ITP cannot continue Single Step Execution after the first breakpoint
Q19 X X NoFix Parity Error in the L1 Cache may cause the processor to hang
Q20 X X NoFix
A 16-bit Address Wrap Resulting from a Near Branch (Jump or Call) May
Cause an Incorrect Address to Be Reported to the #GP Exception Handler
Q21 X Fixed Locks and SMC Detection May Cause the Processor to Temporarily Hang
Q22 X PlanFix Some Front Side Bus I/O Specifications are not Met
Q23 PlanFix Incorrect Physical Address Size Returned by CPUID Instruction
Q24 X X NoFix
Incorrect Debug Exception (#DB) May Occur When a Data Breakpoint is set on
an FP Instruction
Q25 X X NoFix xAPIC May Not Report Some Illegal Vector Errors
Q26 X PlanFix
Incorrect Duty Cycle is Chosen when On-Demand Clock Modulation is Enabled
in a Processor Supporting Hyper-Threading Technology
Q27 X X NoFix
Memory Aliasing of Pages as Uncacheable Memory Type and Write Back (WB)
May Hang the System
Q28 X PlanFix
Enabling No-Eviction Mode (NEM) May Prevent the Operation of the Second
Logical Processor in a Hyper-Threading Technology Enabled Processor
Q29 X X NoFix
Interactions Between the Instruction Translation Lookaside Buffer (ITLB) and
the Instruction Streaming Buffer May Cause Unpredictable Software Behavior
Q30 X PlanFix
STPCLK# Signal Assertion under Certain Conditions May Cause a
System Hang
Q31 X PlanFix
Sequence of Locked Operations Can Cause Two Threads to Receive Stale
Data and Cause Application Hang
Q32 X X NoFix
Using STPCLK and Executing Code From Very Slow Memory Could Lead to a
System Hang
Q33 X X NoFix Processor Provides a 4-Byte Store Unlock After an 8-Byte Load Lock
Q34 X X NoFix
Machine check architecture error reporting and recovery may not work as
expected
Q35 X Fixed EFLAGS.RF May be Incorrectly Set After an IRET Instruction
Q36 X Fixed
Writing the Echo TPR Disable Bit in IA32_MISC_ENABLE May Cause a #GP
Fault
Q37 X Fixed
Incorrect Access Controls to MSR_LASTBRANCH_0_FROM_LIP MSR
Registers
Q38 X X NoFix Recursive Page Walks May Cause a System Hang
Q39 X Fixed
WRMSR to bit[0] of IA32_MISC_ENABLE Register Changes Only One Logical
Processor on a Hyper-Threading Technology Enabled Processor