Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology* on 90 nm Process Technology Specification Update

R
34 Specification Update
Q54.
TPR (Task Priority Register) Updates during Voltage Transitions of Power
Management Events May Cause a System Hang
Problem: Systems with Echo TPR Disable (R/W) bit (bit [23] of IA32_MISC_ENABLE register) set to '0'
(default), where xTPR messages are being transmitted on the system bus to the processor, may
experience a system hang during voltage transitions caused by the power management events.
Implication: This may cause a system hang during voltage transitions of power management events.
Workaround: It is possible for the BIOS to contain a workaround for this erratum. The BIOS workaround disables the
Echo TPR updates on affected steppings.
Status: For the steppings affected, see the Summary Tables of Changes.
Q55.
Running in SMM (System Management Mode) and L1 Data Cache Adaptive Mode
May Cause Unexpected System Behavior when SMRAM is Mapped to Cacheable
Memory
Problem: In a Hyper-Threading Technology-enabled system, unexpected system behavior may occur if a change is
made to the value of the CR3 result from an RSM (Resume From System Management) instruction
while in L1 data cache adaptive mode (IA32_MISC_ENABLES MSR 0x1a0 bit 24). This behavior will
only be visible when SMRAM is mapped into WB/WT cacheable memory on SMM entry and exit.
Implication: This erratum can have multiple failure symptoms including incorrect data in memory. Intel has not
observed this erratum with any commercially available software.
Workaround: Disable L1 data cache adaptive mode by setting the L1 Data Cache Context Mode control (bit 24) of the
IA32_MISC_ENABLES MSR (0x1a0) to 1.
Status: For the steppings affected, see the Summary of Table of Changes
Q56.
Voltage and Frequency Transition May Not Occur if a Voltage Transition is
Interrupted by a Warm Reset
Problem: In an Enhanced Intel SpeedStep
®
technology or Thermal Monitor 2 enabled system, if a voltage and
frequency transition is interrupted by a warm reset and the next transition is to a higher voltage and
frequency then that transition and all subsequent transitions will not be performed.
Implication: When this erratum occurs, the processor will not perform any further transitions and will remain at the
Reset# voltage and frequency. Intel has not observed this erratum with any commercially available
system.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.