Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology* on 90 nm Process Technology Specification Update

32 Specification Update

Q48.

With TF (Trap Flag) Asserted, FP Instruction That Triggers an Unmasked FP

Exception May Take Single Step Trap Before Retirement of Instruction

Problem: If an FP instruction generates an unmasked exception with the EFLAGS.TF=1, it is possible for external

events to occur, including a transition to a lower power state. When resuming from the lower power

state, it may be possible to take the single step trap before the execution of the original FP instruction

completes.

Implication: A Single Step trap will be taken when not expected.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

Q49.

MCA Corrected Memory Hierarchy Error Counter May Not Increment Correctly

Problem: An MCA corrected memory hierarchy error counter can report a maximum of 255 errors. Due to the

incorrect increment of the counter, the number of errors reported may be incorrect.

Implication: Due to this erratum, the MCA counter may report incorrect number of soft errors.

Workaround: None Identified

Status: For the steppings affected, see the Summary Tables of Changes.

Q50.

BTS(Branch Trace Store) and PEBS(Precise Event Based Sampling) May Update

Memory outside the BTS/PEBS Buffer

Problem: If the BTS/PEBS buffer is defined such that:

y The difference between BTS/PEBS buffer base and BTS/PEBS absolute maximum is not an integer

multiple of the corresponding record sizes

y BTS/PEBS absolute maximum is less than a record size from the end of the virtual address space

y The record that would cross BTS/PEBS absolute maximum will also continue past the end of the

virtual address space

Implication: Software that uses BTS/PEBS near the 4G boundary (IA32) or 2^64 boundary (EMT64T mode), and

defines the buffer such that it does not hold an integer multiple of records can update memory outside

the BTS/PEBS buffer.

Workaround: Define BTS/PEBS buffer such that BTS/PEBS absolute maximum minus BTS/PEBS buffer base is

integer multiple of the corresponding record sizes as recommended in the IA-32 Intel® Architecture

Software Developer’s Manual Volume 3A/3B.

Status: For the steppings affected, see the Summary Tables of Changes.