Mobile Intel Pentium 4 Processor Supporting Hyper-Threading Technology* on 90 nm Process Technology Specification Update

20 Specification Update

Q13.

When the Processor is in the System Management Mode (SMM), Debug

Registers May Be Fully Writeable

Problem: When in System Management Mode (SMM), the processor executes code and stores data in the

SMRAM space. When the processor is in this mode and writes are made to DR6 and DR7, the processor

should block writes to the reserved bit locations. Due to this erratum, the processor may not block these

writes. This may result in invalid data in the reserved bit locations.

Implication: Reserved bit locations within DR6 and DR7 may become invalid.

Workaround: Software may perform a read/modify/write when writing to DR6 and DR7 to ensure that the value in the

reserved bits are maintained.

Status: For the steppings affected, see the Summary Tables of Changes.

Q14.

Shutdown and IERR# May Result Due to a Machine Check Exception on a

Hyper-Threading Technology Enabled Processor

Problem: When a Machine Check Exception (MCE) occurs due to an internal error, both logical processors on a

Hyper Threading technology enabled processor normally vector to the MCE handler. However, if one of

the logical processors is in the “Wait for SIPI” state, that logical processor will not have a MCE handler

and will shut down and assert IERR#.

Implication: A processor with a logical processor in the “Wait for SIPI” state will shut down when an MCE occurs on

the other thread.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

Q15.

Processor May Hang Under Certain Frequencies and 12.5% STPCLK# Duty

Cycle

Problem: If a system de-asserts STPCLK# at a 12.5% duty cycle, and the processor is running below 2 GHz, and

the processor thermal control circuit (TCC) on-demand clock modulation is active, the processor may

hang. This erratum does not occur under the automatic mode of the TCC.

Implication: When this erratum occurs, the processor will hang.

Workaround: If use of the on-demand mode of the processor's TCC is desired in conjunction with STPCLK#

modulation, then assure that STPCLK# is not asserted at a 12.5% duty cycle.

Status: For the steppings affected, see the Summary Tables of Changes.