Datasheet

Electrical Specifications
34 Dual-Core Intel® Xeon® Processor 3000 Series Datasheet
I
leak-
High impedance leakage to GND N/A 10 µA
3
C
bus
Bus capacitance per node N/A 10 pF
4
V
noise
Signal noise immunity above 300 MHz 0.1 * V
TT
—V
p-p
Notes:
1.
V
TT
supplies the PECI interface. PECI behavior does not affect V
TT
min/max specifications. Refer
to
Table 2-3 for V
TT
specifications.
2. The input buffers use a Schmitt-triggered input design for improved noise immunity.
3. The leakage specification applies to powered devices on the PECI bus.
4. One node is counted for each client and one node for the system host. Extended trace lengths
might appear as additional nodes.
Table 20. PECI DC Electrical Limits
Symbol Definition and Conditions Min Max Units Notes
1