Intel® 440GX AGPset Design Guide March 1999 Order Number: 290651-001
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Contents 1 Introduction ................................................................................................................1-1 1.1 1.2 1.3 1.4 2 About This Design Guide ..............................................................................1-1 References....................................................................................................1-2 Intel® Pentium® II Processor / Intel® 440GX AGPset Overview ...................1-3 1.3.1 Intel® Pentium® II Processor.............
2.6 2.7 2.8 2.9 3 Design Checklist ........................................................................................................3-1 3.1 3.2 3.3 3.4 3.5 3.6 iv Validation ....................................................................................................2-15 2.6.1 Flight Time Measurement ..............................................................2-15 2.6.2 Signal Quality Measurement..........................................................2-16 Timing Analysis..........
3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20 3.21 3.22 3.23 3.24 4 82371EB (PIIX4E).......................................................................................3-16 3.7.1 PIIX4E Connections.......................................................................3-16 3.7.2 IDE Routing Guidelines..................................................................3-20 3.7.2.1 Cabling..........................................................................3-20 3.7.2.
4.3 5 Debug Features ............................................................................................4-2 4.3.1 Intel® Pentium® II Processor LAI Issue ...........................................4-2 4.3.2 Debug Logic Recommendations......................................................4-4 4.3.2.1 Debug Considerations ....................................................4-5 4.3.3 Debug Layout ..................................................................................4-5 4.3.3.
Figures 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30 2-31 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 4-1 Intel® Pentium® II Processor / Intel® 440GX AGPset System Block Diagram..................................................................................1-4 Major Signal Sections (82443GX Top View).................................................
Tables 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 viii Recommended Trace Lengths for Single Processor Design ........................2-7 Recommended Trace Lengths for Dual Processor Designs2.......................2-8 SET Trace Length Requirements .................................................................
Revision History Date Revision 3/99 -001 Intel® 440GX AGPset Design Guide Description Initial Release.
x Intel® 440GX AGPset Design Guide
1 Introduction
Introduction Introduction 1 This document provides design guidelines for developing Intel® Pentium® II processor / Intel® 440GX AGPset based systems. Motherboard and memory subsystem design guidelines are covered. Special design recommendations and concerns are presented. Likely design issues have been identified and included here in a checklist format to alleviate problems during the debug phase.
Introduction 1.
Introduction 1.
Introduction Intel introduced the Intel® Pentium® II processor as 350/100 and 400/100 speeds with 512 KB L2 cache versions. 1.3.2 Intel® 440GX AGPset • The Intel® 440GX AGPset is the fourth generation chipset based on the Intel® Pentium® Pro processor architecture. It has been designed to interface with the Intel® Pentium® II processor’s system bus at 100 MHz.
Introduction Figure 1-1 shows a block diagram of a typical platform based on the Intel® 440GX AGPset. The 82443GX system bus interface supports up to two Intel ® Pentium® II processors at the maximum bus frequency of 100 MHz. The physical interface design is based on the GTL+ specification and is compatible with the Intel® 440GX AGPset solution. The 82443GX provides an optimized 72-bit DRAM interface (64-bit Data plus ECC). This interface supports 3.3V DRAM technologies.
Introduction 1.3.2.4 PCI Interface The 82443GX PCI interface is 33 MHz Revision 2.1 compliant and supports up to five external PCI bus masters in addition to the I/O bridge (PIIX4E). 1.3.2.5 System Clocking The 82443GX operates the system bus interface at 100 MHz, PCI at 33 MHz and AGP at 66/133 MHz. The 443GX clocking scheme uses an external clock synthesizer which produces reference clocks for the system bus and PCI interfaces.
Introduction Manageability features in each of these four technology areas combine to form the Wired for Management Baseline Specification. A copy of the Wired for Management Baseline Specification can be obtained from: ftp://download.intel.com/ial/wfm/baseline.pdf An on-line Design Guide is available at: http://developer.intel.com/ial/WfM/design/index.htm Future versions of the specification, which preserve today's investments, will be available at this site. 1.3.3.
Introduction 1.3.3.3 Remote Wake-Up If a PC supports a reduced power state, it must be possible to bring the system to a fully powered state in which all management interfaces are available. Typically, the LAN adapter recognizes a special packet as a signal to wake up the system. This reference design utilizes a Wake on LAN (WOL) Header to provide standby power to the NIC and the interface for the wake up signal.
Introduction 1.4.2 General Design Recommendations 1. Intel recommends using an industry standard programmable Voltage Regulator Module (VRM) installed in a VRM header or an onboard programmable voltage regulator designed for Intel® Pentium® II processors. 2. Systems should be capable of varying the system bus to processor core frequency ratio per the System Bus to Core Frequency Multiplier Configuration table of the Intel® Pentium® II processor datasheet.
Introduction 1-10 Intel® 440GX AGPset Design Guide
2 Motherboard Design
Motherboard Layout and Routing Guidelines Motherboard Layout and Routing Guidelines 2 This chapter describes layout and routing recommendations to insure a robust design. Follow these guidelines as closely as possible. Any deviations from the guidelines listed here should be simulated to insure adequate margin is still maintained in the design 2.
Motherboard Layout and Routing Guidelines Figure 2-2 and Figure 2-3 show the proposed component placement for a single processor for both ATX and NLX form factor designs. ATX Form Factor: 1. The ATX placement and layout below is recommended for single (UP) Intel® Pentium® II processor / Intel® 440GX AGPset system design. 2. The example placement below shows 4 PCI slots, 2 ISA slots, 4 DIMM sockets, and one AGP connector. 3.
Motherboard Layout and Routing Guidelines NLX Form Factor: 1. The NLX placement and layout below is recommended for a single (UP) Intel ® Pentium® II processor / Intel® 440GX AGPset system design. 2. The example placement below shows one Slot 1 connector, 4 DIMM sockets, and an AGP compliant device down. 3. For an NLX form factor design, the AGP compliant graphics device may readily be integrated on the motherboard (device down option). 4.
Motherboard Layout and Routing Guidelines Figure 2-4. Four Layer Board Stack-up Z = 60 ohms Primary Signal Layer (1/2 oz. cu.) 5 mils 47 mils 5 mils Z = 60 ohms PREPREG CORE PREPREG Ground Plane (1 oz. cu.) Power Plane (1 oz. cu) Secondary Signal Layer (1/2 oz. cu) Total board thickness = 62.6 Note: The top and bottom routing layers specify 1/2 oz. cu. However, by the time the board is plated, the traces will end about 1 oz. cu.
Motherboard Layout and Routing Guidelines Figure 2-6. Six Layer Board Stack-up With 3 Signal Planes and 3 Power Planes Primary Signal Layer (1/2 oz. cu.) Z = 60 ohms 5 mils Z = 59 ohms PREPREG 18 mils CORE 8 mils PREPREG 18 mils 5 mils Z = 60 ohms CORE PREPREG Ground Plane (1 oz. cu.) Inner Layer #1 (1 oz. cu.) Power Plane #1 (1 oz. cu) Power Plane #2 (1 oz. cu) Secondary Signal Layer (1/2 oz. cu) Total board thickness = 62.
Motherboard Layout and Routing Guidelines 2.3.1 GTL+ Description GTL+ is the electrical bus technology used for the Intel® Pentium® Pro processor and Intel® Pentium® II processor system bus. GTL+ is a low output swing, incident wave switching, opendrain bus with external pull-up resistors that provide both the high logic level and termination at the end of the bus. The complete GTL+ specification is contained in the Pentium II processor databook.
Motherboard Layout and Routing Guidelines 2.3.3.2 Single Processor Recommended Trace Lengths Single processor trace length recommendations are summarized in Table 2-1. The recommended lengths are derived from the parametric sweeps and Monte Carlo analysis described in the following section. Table 2-1. Recommended Trace Lengths for Single Processor Design Trace Minimum Length Maximum Length L1 1.50” 6.75” 1 L3 0.00” 1.50” L4 0.00” 2.50” 2 NOTE: 1.
Motherboard Layout and Routing Guidelines 2.3.4 Dual Processor Systems 2.3.4.1 Dual Processor Network Topology and Conditions Figure 2-9. Recommended Topology for Dual Processor Design Intel® 440GX AGPset L3 L5 Slot 1 Slot 1 L4 2.3.4.2 Dual Processor Recommended Trace Lengths The recommended trace lengths for dual processor designs are summarized in Table 2-2.
Motherboard Layout and Routing Guidelines In the SET topology, the only termination is on the Intel® Pentium® II processor substrate. There is no termination present at the other end of the network. Due to the lack of termination, SET exhibits much more ringback than the dual terminated topology. Extra care is required in SET simulations to make sure that the ringback specs are met under the worst case signal quality conditions.
Motherboard Layout and Routing Guidelines 2.3.6 Additional Guidelines 2.3.6.1 Minimizing Crosstalk The following general rules will minimize the impact of crosstalk in the high speed GTL+ bus design: • Maximize the space between traces. Maintain a minimum of 0.010” between traces wherever possible. It may be necessary to use tighter spacings when routing between component pins. • Avoid parallelism between signals on adjacent layers.
Motherboard Layout and Routing Guidelines 2.3.7 Design Methodology Intel recommends using the following design methodology when designing systems based on one or two Intel® Pentium® II processors and one Intel® 440GX AGPset. The methodology evolved from Intel’s experience developing and validating high speed GTL+ bus designs for the Intel® Pentium® Pro and Intel® Pentium® II processors. The methodology provides a step-by-step process which is summarized in Figure 2-12.
Motherboard Layout and Routing Guidelines Figure 2-12. GTL+ Design Process Establish System Performance Requirements (Timing Analysis) Define Topologies Perform Pre-Layout Simulations (Sensitivity Analysis) Define Routing Rules Place & Route Board Perform Post-Layout Simulations (Verification) Meet Requirements? No Yes Validate Design 2.3.8 Performance Requirements Prior to performing interconnect simulations, establish the minimum and maximum flight time requirements.
Motherboard Layout and Routing Guidelines Section 2.7, “Timing Analysis” on page 2-17 describes the timing analysis for the 100 MHz host bus in more detail. Table 2-4 provides recommended flight time specifications for single and dual Intel® Pentium® II processor systems. Flight times are measured at the Intel® Pentium® II processor edge fingers.
Motherboard Layout and Routing Guidelines The methodology that Intel recommends is known as “Sensitivity Analysis”. In sensitivity analysis, interconnect parameters are varied to understand how they affect system timing and signal integrity. Sensitivity analysis can be further broken into two types of analysis, parametric sweeps and Monte Carlo analysis, which are described below. Figure 2-13. Pre-layout simulation process Interconnect Simulations (Transmission-Line) 1.75v 1.75v 1.75v 1.25v 0.25v 1.
Motherboard Layout and Routing Guidelines 2.5.1 Crosstalk and the Multi-Bit Adjustment Factor Coupled lines should be included in the post-layout simulations. The flight times listed in Table 2-4 apply to single bit simulations only. They include an allowance for crosstalk. Crosstalk effects are accounted for, as part of the multi-bit timing adjustment factor, Tadj, that is defined in Table 2-8. The recommended timing budget includes 400 ps for the adjustment factor.
Motherboard Layout and Routing Guidelines Table 2-5.
Motherboard Layout and Routing Guidelines 2.7 Timing Analysis To determine the available flight time window perform an initial timing analysis. Analysis of setup and hold conditions will determine the minimum and maximum flight time bounds for the host bus. Use the following equations to establish the system flight time limits. Table 2-7.
Motherboard Layout and Routing Guidelines Notice that the timing equations include an extra term to account for the delay due to routing of the BCLK trace on the processor substrate from the processor edge fingers and the processor core. Adding the BCLK adjustment to the timing calculations between processor and chipset guarantees host clock synchronization between the AGPset and processor core. The minimum and maximum values for this term are contained in Table 2-9.
Motherboard Layout and Routing Guidelines 2.8 AGP Layout and Routing Guidelines For the definition of AGP Interface functionality (protocols, rules and signaling mechanisms, as well as the platform level aspects of AGP functionality), refer to the latest AGP Interface Specification rev 1.0 and the AGP Platform Design Guide. These documents focus only on specific Intel® 440GX AGPset platform recommendations for the AGP interface. In this document the term “data” refers to AD[31:0], C/BE[3:0]# and SAB[7:0].
Motherboard Layout and Routing Guidelines It is always best to reduce the line length mismatch wherever possible to insure added margin. It is also best to separate the traces by as much as possible to reduce the amount of trace to trace coupling. Table 2-13. Source Synchronous Motherboard Recommendations Width:Space Trace Line Length Line Length Matching 1:1 (Data) / 1:2 (Strobe) Data / Strobe 1.0 in < line length < 4.5 in -0.5 in, strobe longest trace 1:2 Data / Strobe 1.0 in < line length < 9.
Motherboard Layout and Routing Guidelines Figure 2-15. On-board AGP Compliant Device Layout Guidelines Always 1:2 Strobe Routing AGP Compliant Graphics Device 82443GX 1.0” - 4.5” 1:1 (Data) Routing 1” - 12” 1:2 (Data) Routing For trace lengths that are between 1.0 inch and 4.5 inches, a 1:1 trace spacing is recommended for data lines. The strobe requires a 1:2 trace spacing. This is for designs that require less than 4.5 inches between the AGP device and the AGP target.
Motherboard Layout and Routing Guidelines Some of the control signals require pull-up resistors to be installed on the motherboard. AGP signals must be pulled up to VCC3.3 using 8.2K to 10K ohm pull-up resistors (refer to Section 3.5.1, “82443GX Interface” on page 3-10). Pull-up resistors should be discrete resistors, as resistor packs will need longer stub lengths and may break timing. The stub to these pull-up resistors needs to be controlled. The maximum stub length on a strobe trace is < 0.1 inch.
Motherboard Layout and Routing Guidelines Data Register PLL Control Clock SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM Figure 2-17. Registered SDRAM DIMM Example Register There are also “population” rules which need to be observed. To properly adjust memory timings for 100 MHz operation, it is asked of the OEM and end user to populate the motherboard starting with the DIMM located the furthest from the 82443GX. 2.9.1.
Motherboard Layout and Routing Guidelines Figure 2-18. Matching the Reference Planes and Adding Decoupling Capacitor 2.9.1.3 Trace Width vs. Trace Spacing To minimize the crosstalk, a 1:2 trace width vs. trace spacing routing (e.g., 6 mils on 9 mils or 5 mils on 10 mils) should be used for all memory interface signals. 2.9.2 Memory Layout & Routing Guidelines Figure 2-19.
Motherboard Layout and Routing Guidelines . Table 2-18. FET Switch DQ Route Example 1.1” - 2.0” 0.6” 0.7” - 2.4 ” 0.6” FET SW 0.3” - 1.0” 82443GX v004 Figure 2-20. Motherboard Model—Data (MDxx), 4 DIMMs 0.7” - 2.4” FET Switch 16212 Intel® 440GX AGPset Design Guide 0.3” - 1.0” 1.1” - 2.0” 0.4” - 0.6” DIMM Module 4 DIMM Module 1 DIMM Module 2 0.4” - 0.
Motherboard Layout and Routing Guidelines Figure 2-21. Motherboard Model—DQMA[0,2:4,6:7], 4 DIMMs 1.0” - 3.25” 82443GX 0.4” - 0.6” DIMM Module 4 0.4” - 0.6” DIMM Module 3 DIMM Module 2 DIMM Module 1 0.4” - 0.6” Figure 2-22. Motherboard Model—DQM_A[1,5], 4 DIMMs 1.0” - 3.25” 0.4” - 0.6” DIMM Module 2 DIMM Module 1 82443GX Figure 2-23. Motherboard Model—DQM_A[1,5], 4 DIMMs 1.0” - 3.25” 0.4” - 0.
Motherboard Layout and Routing Guidelines Figure 2-24. Motherboard Model—DQM_B[1,5], 4 DIMMs 1.0” - 3.25” 0.4” - 0.6” DIMM Module 4 DIMM Module 3 82443GX Figure 2-25. Motherboard Model—CS_A#/CS_B#, 4 DIMMs 1.0” - 4.0” 82443GX DIMM Module x Figure 2-26. Motherboard Model—SRAS_A#, 4 DIMMs 1.0” - 3.0” 0.4” - 0.
Motherboard Layout and Routing Guidelines Table 2-19. Motherboard Model: SRAS_B#, 4 DIMMs 1.0” - 3.0” 0.4” - 0.6” DIMM Module 4 DIMM Module 3 82443GX Table 2-20. Motherboard Model: SCAS_A#, 4 DIMMs 1.0” - 3.0” 0.4” - 0.6” DIMM Module 2 DIMM Module 1 82443GX Table 2-21. Motherboard Model: SCAS_B#, 4 DIMMs 1.0” - 3.0” 0.4” - 0.
Motherboard Layout and Routing Guidelines Table 2-22. Motherboard Model: WE_A#, 4 DIMMs 1.0” - 3.0” 0.4” - 0.6” DIMM Module 2 DIMM Module 1 82443GX Table 2-23. Motherboard Model: WE_B#, 4 DIMMs 1.0” - 3.0” 0.4” - 0.6” DIMM Module 4 DIMM Module 3 82443GX Table 2-24. Motherboard Model: MA_A[14:0], 4 DIMMs 1.0” - 3.0” 0.4” - 0.
Motherboard Layout and Routing Guidelines Table 2-25. Motherboard Model: MA_B[12,11,9:0]#, MA_B[14,13,10], 4 DIMMs VCC3 0.4” - 0.6” 1.0” - 3.0” 82443GX 2.9.3 Max stub to 10 KΩ pullup/pulldown at end of line: 0.2” - MAB12# 0.5” - MAB[11,9]# (only applies to straps) DIMM Module 4 DIMM Module 3 10 KΩ 4 DIMM Routing Guidelines [NO FET] Figure 2-27. Motherboard Model—Data (MDxx) Lines, 4 DIMMs (No FET) 2” - 3” 82443GX 0.4” DIMM Module 4 DIMM Module 2 DIMM Module 1 0.2” DIMM Module 3 0.2” 0.
Motherboard Layout and Routing Guidelines Because of the specifics of an ATX layout, it is recommended that the PIIX4E component is at the “END” of the PCI bus, as shown in Figure 2-28. This insures proper “termination” of the PCI Bus signals. Figure 2-28. PCI Bus Layout Example 82443GX PIIX4E Decoupling Guidelines: Intel® 440GX AGPset Platform 2.9.5 Decoupling caps should be placed at the corners of the 443GX(BGA Package). A minimum of four 0.1uF and four 0.01 uF are recommended.
Motherboard Layout and Routing Guidelines 2.9.6 Intel® 440GX AGPset Clock Layout Recommendations 2.9.6.1 Clock Routing Spacing A Intel® Pentium® II processor / Intel® 440GX AGPset platform requires a clock synthesizer for supplying 100 MHz system bus clocks, PCI clocks, APIC clocks, and 14 MHz clocks. These clocks are supplied by a CK100 clock synthesizer as defined by the CK97 clock/driver specification.
Motherboard Layout and Routing Guidelines 2.9.6.3 PCI Clock Layout PCI clock nets should be routed a point-to-point connections with a 22 Ohm series resistor that is to be placed as close to the output pins on the clock driver as possible (<0.5”). Layout guidelines: Match trace lengths to the longest trace. Net 2.9.6.4 Trace length min max Substrate Clock chip - PCI connector H + 4.8” 1.0” 12.5” 2.5” Clock chip - PIIX4E H + 7.3” 1.0” 15.0” NA Clock chip -440GX H + 7.3” 1.0” 15.
Motherboard Layout and Routing Guidelines 2.9.6.5 AGP Clock Layout Series Termination: 22 Ohm series termination should be used for the AGP clocks. Layout guidelines: The feedback clock trace length equals the standard clock motherboard trace length plus the card trace length. Figure 2-31. AGP Clock Layout BX 22ohm GCLKOUT AGPCLK 22ohm GCLKIN Net 22 Ohm resistor - AGP connector 22 Ohm resistor - 82443GX (feedback) Note: 2-34 Trace Length Min Max Card Trace Length A 0.5” 12” ~3.3” A + 3.
3 Design Checklist
Design Checklist Design Checklist 3.1 3 Overview The following checklist is intended to be used for schematic reviews of Intel® 440GX AGPset desktop designs. It does not represent the only way to design the system, but provides recommendations based on the Intel® 440GX AGPset reference platform. 3.2 Pull-up and Pull-down Resistor Values Pull-up and pull-down values are system dependent.
Design Checklist Figure 3-1. Pull-up Resistor Example VccPU MIN RMAX VIH MIN ILeakage MAX VccPU MAX RMIN VIL MAX IOLMAX 3.3 Intel® Pentium® II Processor Checklist 3.3.1 Intel® Pentium® II Processor Table 3-1. Slot Connectivity (Sheet 1 of 3) Processor Pin 100/66# Pin Connection UP: Connected to CK100. 10K ohm series resistor to MAB#12. 200 ohm pull-up to 3.3V at CK100. DP: connect between CPUs (Logic may be provided to detect a frequency match).
Design Checklist Table 3-1. Slot Connectivity (Sheet 2 of 3) Processor Pin Pin Connection DBSY# UP: Connect to 82443GX; DP: Connect CPUs and 82443GX. DEFER# UP: Connect to 82443GX; DP: Connect CPUs and 82443GX. DEP[7:0] No connect. DRDY# UP: Connect to 82443GX; DP: Connect CPUs and 82443GX. EMI Connect to GND. FERR# UP: Connect to PIIX4E, 220 ohm pull-up to 2.5V. DP: Connect CPUs and PIIX4E, 220 ohm pull-up to 2.5V. FLUSH# UP: 510 ohm pull-up to 2.5V. DP: Connect CPUs and 510 ohm pull-up.
Design Checklist Table 3-1. Slot Connectivity (Sheet 3 of 3) Processor Pin Pin Connection UP: Connected to ITP. 150 ohm pull-up to 2.5V. TDO DP: Connected to jumpers between ITP and CPU signals. See DP schematics for details. UP: Connected to ITP. 150 ohm - 330 ohm pull-up to 2.5V. TDI DP: Connected to jumpers between ITP and CPU signals. See DP schematics for details. TESTHI UP: 4.7K ohm pull-up to 2.5V. DP: Connect CPUs and 4.7K ohm pull-up to 2.5V. THERMTRIP# UP: NC if not used.
Design Checklist 3.3.2 Intel® Pentium® II Processor Clocks • Include a circuit for the system bus clock to core frequency ratio to the processor. The ratio should be configurable as opposed to hard wired. The bus frequency select straps will be latched on the rising edge of CRESET#. • CRESET# is used as the selection signal for muxing A20M#, IGNNE#, INTR, and NMI with the processor bus/core frequency selection jumpers. A ‘244 buffer maybe used as a mux.
Design Checklist used by other logic requiring CMOS/TTL logic levels. The VID lines on the Slot 1 connector are 5V tolerant. • Vcc (±5%) should be provided to the Slot 1 signal Vcc pin B109. This power connection is not used by the Intel® Pentium® II processor. It is required for the Slot 1 EMT tool and may be required by future Boxed processors. • The JTAG port must be properly terminated even if it is not used. See the Debug Recommendations for further information that may affect these resistor values.
Design Checklist 3.3.4 Uni-Processor (UP) Slot 1 Checklist • A UP system must connect BREQ0# of the Slot 1 connector to the 82443GX’s BREQ0# signal. This will assign an agent ID of 0 to the processor. BREQ1# on the Slot 1 connector is left as a no connect. • For a UP design, one set of GTL+ termination resistors (56 ohm) are recommended on the motherboard (dual ended termination). The second set of terminations are provided on the Intel® Pentium® II processor.
Design Checklist 3.4 Intel® 440GX AGPset Clocks 3.4.1 CK100 - 100 MHz Clock Synthesizer • The system clock which provides 100 MHz to the processor and the Intel® 440GX AGPset, and the clocks for the APIC must be +2.5V. • If implemented in the clock chip, pin 28, when strapped low, provides a spread spectrum modulation effect which may help reduce EMI. The modulation will be “down spread” only, meaning that the nominal 100/66 MHz frequencies will be modulated 0.25% to 0.5% below 100/66.
Design Checklist 3.4.2 CKBF - SDRAM 1 to 18 Clock Buffer • A 4.7K ohm pull-up to VCC3.3 on the OE pin is needed to enable the buffer. • Note that DCLKRD pin has been changed to a no connect (NC). The DCLKRD functionality has been combined with DCLKWR. If desire to remove the trace going to DCLKRD pin, the capacitor value should be adjusted to compensate for the capacitance change. • An I2C interface is provided which allows the BIOS to disable unused SDRAM clocks to reduce EMI and power consumption.
Design Checklist 3.5 82443GX Host Bridge 3.5.1 82443GX Interface Table 3-4. 82443GX Connectivity (Sheet 1 of 3) SIGNAL CONNECTION AD#[31:0] Connected to PCI bus. ADS# Connected to CPUs. AGPREF Connected to be 0.4 of VCC3.3. Can be performed by a voltage divider. BNR# Connected to CPUs. BPRI# Connected to CPUs. BREQ0# Connected to CPUs. GXPWROK Connected to PIIX4E PWROK pin. C/BE[3:0]# Connected to PCI bus. FENA 4DIMM Design: Connected to FET-switches as an enable pin.
Design Checklist Table 3-4. 82443GX Connectivity (Sheet 2 of 3) SIGNAL GADSTBA, GADSTBB, GDEVSEL#, GFRAME#, GGNT#, GIRDY#, GREQ#, GSTOP#, GTRDY#, CONNECTION 8.2K ohm pull-ups to 3.3V. Connected to AGP connector. GPAR 100K ohm pull-down required. Connect to AGP connector. GTLREFA, GTLREFB GTL buffer voltage reference input (1.0V = 2/3 vtt) HA[31:3]# Connected to CPUs. HCLKIN Connected to CK100 through 22 ohm series resistor. HD[63:0]# Connected to the CPUs. HIT#, HITM# Connected to CPUs.
Design Checklist Table 3-4. 82443GX Connectivity (Sheet 3 of 3) SIGNAL CONNECTION TRDY# 2.7K ohm pull-up to 5V. Connected to PCI bus. VTTA, VTTB GTL threshold voltage for early clamps. WE[B:A]# Each connected to up to 2 DIMMs. WSC# UP: Leave as a NC. DP: Connected to IOAPIC. No pull-up resistor is needed. • GTLREFx pins are driven from independent voltage dividers which set the GTLREFx pins to VTT*2/3 using a 75 ohm and 150 ohm resistor ratio.
Design Checklist — TMS (connector pin A3) and TDI (connector pin A4) should be independently bussed and pulled up with 5K ohm (approximate) resistors. — TRST# (connector pin A1) and TCK (connector pin B2) should be independently bussed and pulled down with 5K ohm (approximate) resistors. — TDO (connector pin B4) should be left open. 3.5.4 82443GX AGP Interface • The following will help reduce the AGPREF margin needed when data is being written or read • • • • • • via the AGP bus interface.
Design Checklist 3.6 Intel® 440GX AGPset Memory Interface 3.6.1 SDRAM Connections Table 3-6.
Design Checklist 3.6.2 DIMM Solution With FET Switches • With existing 64Mbit technology, 512 MB, 1 GB and 2 GB support for servers and workstations must have 4 double sided DIMMs. • 500 ohm - 1K ohm pull-down resistors on each of the second inputs (1A2, 2A2, etc.) are recommended on the FET switches (500 ohms is recommended based on simulation) to prevent a direct short to ground while switching. Figure 3-3.
Design Checklist 3.7 82371EB (PIIX4E) 3.7.1 PIIX4E Connections Table 3-7. PIIX4E Connectivity (Sheet 1 of 4) Signal Names Connection 48MHz Connect to CK100 through a 22 ohm series resistor. A20GATE Connected to SIO. 8.2K ohm pull-up to VCC3. A20M# Part of CPU/bus frequency circuit. 2.7K ohm pull-up to VCC3. AD[31:0] Connect to PCI slots and 82443GX. AEN Connect to SIO and ISA slots. APICACK# / GPO12 UP: Leave as a NC. DP: Connect to IOAPIC. APICCS# / GPO13 UP: Leave as a NC.
Design Checklist Table 3-7. PIIX4E Connectivity (Sheet 2 of 4) Signal Names Connection IOCHCK# Connected to ISA slots. 4.7K ohm pull-up to VCC. IOCHRDY Connected to ISA slots and Ultra I/O. 1K ohm pull-up to VCC. IOCS16# Connected to ISA slots. 1K ohm pull-up to VCC. IOR# Connected to ISA slots, Ultra I/O, LM79. 8.2K ohm pull-up to VCC. IOW# Connected to ISA slots, Ultra I/O, LM79. 8.2K ohm pull-up to VCC. IRDY# 2.7K ohm pull-up to 5V or 10K ohm pull-up to 3V.
Design Checklist Table 3-7. PIIX4E Connectivity (Sheet 3 of 4) Signal Names Connection PHLD# Connected to 82443GX. 8.2K ohm pull-up to VCC3. PHLDA# Connected to 82443GX. 8.2K ohm pull-up to VCC3. PIORDY Connected to IDE through 47 ohm series resistor. 1K ohm pull-up to VCC on the PIIX4E side of the series resistor. PIRQ[D:A]# 2.7K ohm pull-up to 5V or 10K ohm pull-up to 3V. Connect between 443GX, PCI slots, and PIIX4E. PIRQ[A:B]# also go to AGP. DP: PIRQ[A:D]# connected to IOAPIC.
Design Checklist Table 3-7. PIIX4E Connectivity (Sheet 4 of 4) Signal Names SMBCLK, Connection SMBDATA Connect to all devices on SMBus. 2.7K ohm pull-up to VCC3. This value may need to be adjusted based on bus loading. SMEMR#, SMEMW# Connected to ISA slots. 1K ohm pull-up to VCC. SMI# 430 ohm pull-up to 2.5V. This is an open drain output from PIIX4E. UP: Connected to CPU. DP: Connected to IOAPIC. SPKR Connect to speaker circuit. STOP# 2.7K ohm pull-up to 5V or 10K ohm pull-up to 3V.
Design Checklist 3.7.2 IDE Routing Guidelines This section contains guidelines for connecting and routing the PIIX4E IDE interface. The PIIX4E has two independent IDE channels. This section provides guidelines for IDE connector cabling and motherboard design, including component and resistor placement, and signal termination for both IDE channels.
Design Checklist One resistor per IDE connector is recommended for all signals. For signals labeled as 22-47Ω, the correct value should be determined for each unique motherboard design, based on signal quality. Figure 3-4. Series Resistor Placement for Primary IDE Connectors 74HCT14 22 - 47 ohm RSTDRV Reset# 10K ohm PDD7 33 ohm PDD[15:0] 33 ohm PDA[2:0] 33 ohm PDCS1# 33 ohm PDCS3# 33 ohm PDIOW# 22 - 47 ohm PDDACK# 22 - 47 ohm IRQ14 33 ohm PDDREQ 5V 5.
Design Checklist 3.7.3 PIIX4E Power And Ground Pins • Vcc, Vcc(RTC), Vcc(SUS), and Vcc(USB) must be tied to 3.3V. • VREF must be tied to 5V in a 5V tolerant system. This signal must be power up before or simultaneous to Vcc, and it must be power down after or simultaneous to Vcc. For the layout guidelines, refer to the Pin Description section of the PIIX4E datasheet. The VREF circuitry can be shared between 82443GX and the PIIX4E.
Design Checklist Third, if the design currently uses an in-line active gate/buffer on PCIRST# to drive the PCI bus, consider removal of this gate/buffer entirely. The PIIX4/PIIX4E is designed to drive the entire PCI bus. Table 3-10. Non-PIIX4E PCI Signals SIGNAL (5V PCI environment) 2.7K ohm pull-up resistors to 5V. ACK64#, (3V PCI environment) 10K ohm pull-up resistors to 3.3V. PERR#, PERR# and PLOCK# can be connected together across PCI slots and pulled up by single resistor.
Design Checklist 3.11 USB Interface • Contact your local Intel Field Sales representative for the following Application Note: 82371AB PIIX4 Application Note #1: USB Design Guide And Checklist Rev 1.1. This document discusses details of the PIIX4/PIIX4E implementation of the Universal Serial Bus. Included in the discussion are motherboard layout guidelines, options for USB connector implementation, USB clocking guidelines and a design checklist.
Design Checklist 3.13 Flash Design 3.13.1 Dual-Footprint Flash Design New features are coming to the PC continue to increase the size of BIOS code, pushing the limits of the 1 Mbit boundary. OEMs have already converted many PC designs to 2 Mbit BIOS and higher, and more will follow. Since it is difficult to predict when BIOS code will exceed 1 Mbit, OEMs should design motherboards to be flexible.
Design Checklist Following are general layout guidelines for using the Intel’s boot block flash memories (28F001GX/28F002BC) in the system: • If adding a switch on VPP for write protection, switch to GND instead of VCC. • Connect the DU pin of the 2Mbit devices to GND if anticipating to use the Intel SmartVoltage boot block flash memory family in the future. • Use A16 inversion for 1Mbit devices and A17 inversion for 2Mbit devices to differentiate between recovery and normal modes.
Design Checklist (WP# pin not available on 8-Mbit 44-lead PSOP. In this package, treat as if the WP# pin is internally tied low, effectively eliminating the last row of the table below.) • Use either A16 or A17 inversion for both the 2Mbit or 4Mbit to differentiate between recovery and normal modes. • If migrating a BV design to the lower cost B5 device, Application Brief AB-65 “Migrating SmartVoltage Boot Block Flash Designs to Smart 5 Flash” is available (Order#292194). Table 3-13.
Design Checklist Figure 3-7. Interfacing Intel’s Flash with PIIX4E in Desktop SD[7:0] SD[7:0] +5V DQ[7:0] Vpp PIIX4E N.C. DQ[14:8] 0.01uf PIIX4 SUSA# GPO[x] 3.14 2/4Mbit BV/B5 Flash RP# Vcc WP# SA[17:0] SA[17:0] MEMW# WE# MEMR# OE# BIOSCS# CE# Vcc 0.01 uf BYTE# System and Test Signals • 8.2K ohm pull-up resistor is recommended on the TEST# pin of the PIIX4E. 3.15 Power Management Signals • A power button is required by the ACPI specification.
Design Checklist standby voltage is not provided by the power supply, then tie PWROK signal on the PIIX4E to the RSMRST# signal. • If an 8.2K ohm resistor divider is used to divide the RSMRST# signal down to a 3V level for input to the PIIX4E, the rise time of this signal will be approximately 170ns (based on the input capacitance of the PIIX4E), which is within the maximum 250ns requirement of the PIIX4E.
Design Checklist • The system reset button has typically been connected indirectly to the PWROK input of the PIIX4/PIIX4E. This technique will not reset the suspend well logic, which includes the SMBus Host and Slave controllers. To reset the hardware in the suspend well, the reset button should be connected to the RSMRST# input of the PIIX4/PIIX4E. Assertion of RSMRST#, via a reset button, will result in a complete system reset.
Design Checklist • Poll the power button status bit during POST while SMIs are not loaded and go directly to softoff if it gets set. • • • • • Always install an SMI handler for the power button that operates until ACPI is enabled. Emergency Override: Pressing the power button for 4 seconds goes directly to S5. This is only to be used in EMERGENCIES when software is locked-up. This will cause user data to be lost in most cases.
Design Checklist be stubbed off the trace run and must be as close as possible to the PIIX4/PIIX4E. The capacitor must be no further than 0.5 inch from the PIIX4/PIIX4E. If a stub is required, it should be kept to a few mm maximum length. The ground connection should be made through a via to the ground plane, with no or minimal trace between the capacitor pad and the via. — Place the battery, 1K Ohm series current limit resistor, and the common-cathode isolation diode very close to the PIIX4/PIIX4E.
Design Checklist PIIX4E. For ACPI compliance, this signal must be connected to the IOAPIC. There are two different routing options: — INTIN9: IRQ9OUT# can be connected to INTIN9 on the IOAPIC. The ACPI BIOS will report to the OS that the SCI uses IRQ9 for both PIC and APIC enabled platforms. However, for this solution ISA IRQ9 must be left unconnected. The could create an ISA legacy incompatibility with ISA cards that must only use IRQ9. Note that this conflict exists in all PIC enabled systems.
Design Checklist • Analog inputs feed inverting op-amp stages, useful for monitoring power supply regulation. • The LM79 is a 5V part, however SMBus requires a 3.3V interface. Level translation circuitry is required. See the reference schematics for an example circuit. • CHASSIS_INTRU and FAN3 are pulled down and SMI_IN# is pulled up with 10K ohm resistors. • The LM79 is connected to a programmable chip select on the PIIX4E. This assumes that the LM79 is tied to the X-Bus.
Design Checklist 3.18.4 Wake On LAN (WOL) Header • A 3-pin WOL header interconnects the NIC and motherboard, and requires a 5VSB to pin1. • The WOL supports the MP_Wakeup pulse, allowing it to turn on the system via a signal pulse. The LID input on the PIIX4E requires a 16ms debounce signal. • The MP_Wakeup signal, to the PIIX4E LID pin, requires a 5V to 3V translation. NOTE: The LID pin will be configured as an active high signal through BIOS for this specific implementation.
Design Checklist 3.19.2 Design Considerations • For UP systems to support both the current Intel® Pentium® II processor and future processors, it is highly recommended that storage space for two (or more) BIOS Updates be provided. This will allow manufacturing flexibility to install either processor, the BIOS should detect the processor and load the correct BIOS Update.
Design Checklist 3.21.1 Design Considerations • The Intel® Pentium® II processor retention mechanism, retention mechanism attach mount and heat sink support is an optional support structure for retaining the Slot 1 processor in the system during shock and vibration situations. If these Intel enabled retention solutions are used, the motherboard keep out zones and mounting hole requirements must be met. See the Intel® Pentium® II Datasheet for details.
Design Checklist 3.23 Layout Checklist 3.23.1 Routing and Board Fabrication • VRM 8.2 Support: Is the VccCORE trace/power plane sufficient to ensure VccCORE meets specification. See the Intel® Pentium® II Datasheet for trace/power plane resistance and length requirements. • • • • • VTT should be routed with at least a 50 mil (1.25mm) wide trace. VREF traces should be isolated to minimize the chance of cross-talk.
4 Debug Recommendations
Debug Recommendations Debug Recommendations 4 This chapter provides tool information, logic suggestions, technical support options and a summary of the problems which have been found to be associated with system debug. Although not comprehensive in scope, the recommendations are included to preclude unnecessary expenditures of time and effort during the early stages of debug.
Debug Recommendations Contact your local Intel Field Sales representative to complete the proper software license agreement and non-disclosure agreement required to receive the ITP. 4.2.3 Bus Functional Model (BFM) A bus functional model for the Intel ® Pentium® II processor system bus is available from third party vendors and requires a special non-disclosure agreement.
Debug Recommendations Figure 4-1. LAI Probe Input Circuit The extra loading of the LAI562 requires stronger pull-up values on the target system. However, due to the current limitations of some signal drivers, this stronger value may not be feasible.
Debug Recommendations Inputs to the Slot 1 connector, from system logic (assuming a 14mA driver): • • • • • • PWRGOOD 150 - 330 ohm INIT# 150 - 330 ohm LINT[0]/INTR 150 - 330 ohm LINT[1]/NMI 150 - 330 ohm IGNNE# 150 - 330 ohm A20M# 150 - 330 ohm Bi-directional signal to/from the Slot 1 connector: • PICD[0]# • PICD[1]# 150 ohm 150 ohm Inputs to the Slot 1 connector, only pull-up: •FLUSH# 4.3.
Debug Recommendations 4.3.2.1 Debug Considerations • As technology drives better low power modes, the VccCORE current demand could approach 0 Amps. This may cause a regulator to go out of regulation. Place pads for a load resistance on the VccCORE regulator in the event the regulator cannot approach 0 Amps. • After meeting the guidelines in the Intel® Pentium® II Processor Datasheet, add as many extra high frequency and bulk decoupling capacitance sites as will fit near the processor slot.
Debug Recommendations • The Global Descriptor Table (GDT) must be aligned. The GDT must be located on a DWord boundary, or else setting the PE bit and branching will cause a SHUTDOWN transaction. • The ITP “pins” command may be used to check reset configuration pin states. Be aware, however, that observing pin state during reset will not reveal anything about the stability or timing of the configuration signals around the reset edge.
5 Third Party Vendors
Third-Party Vendor Information 5 Third-Party Vendor Information This design guide has been compiled to give an overview of important design considerations while providing sources for additional information. This chapter includes information regarding various third-party vendors who provide products to support the Intel® 440GX AGPset. The list of vendors can be used as a starting point for the designer.
Third-Party Vendor Information 5.1.1 Voltage Regulator Modules The following vendors are developing DC-DC converter modules for Intel ® Pentium® II processor voltage and current requirements per the VRM 8.2 DC-DC Converter Design Guidelines. Table 5-4. Voltage Regulator Modules Supplier, Intel CNDA Contact Phone Celestica Dariusz Basarab 416-448-5841 Corsair Microsystems John Beekley 408-559-1777 Delta Electronics Colin Weng North America: Delta Products Corp.
Third-Party Vendor Information 5.2 Intel® 440GX AGPset 5.2.1 Clock Drivers Intel has supplied specifications to clock driver vendors, including the following. The specifications define requirements for Intel® Pentium® II processor-based systems with Intel® 440GX AGPset. Intel tests some clock devices to verify the ability of the industry to meet the Intel specification; there is no formal component qualification. Table 5-6. Clock Driver Vendors Supplier, Intel CNDA 5.2.
Third-Party Vendor Information 5.3 Other Processor Components 5.3.1 Slot 1 Connector Public information; see Intel® Pentium® II Processor Support Components Web page: http://developer.intel.com/design/PentiumII/components/index.htm 5.3.2 Mechanical Support Public information; see Intel® Pentium® Processor Support Components Web page. These components include the Slot 1 retention mechanism, dual retention mechanism, retention mechanism attach mount, and heat sink supports. 5.3.
A Reference Design Schematics
Intel® 440GX AGPset Platform Reference Design Intel® 440GX AGPset Platform Reference Design A This section describes the DP/Intel® 440GX AGPset 4-DIMM Reference Design Schematics. The description of each schematic page is named by the logic block shown on that page. The numbers after the schematic page name list the page number of the dual processor design. Cover Sheet 1 The Cover Sheet shows the Schematic page titles, page numbers and disclaimers.
Intel® 440GX AGPset Platform Reference Design 82443GX Component (System bus and DRAM Interfaces) 8 This page shows the 82443GX component, System bus and DRAM Interfaces. The 82443GX connects to the lower 32 bits of the CPU address bus and the CPU control signals, and generates DRAM control signals for the memory interface. In this design, the 82443GX is configured to interface to a memory array of 4 DIMMs for a DP design. The CKBF is also shown on this page.
Intel® 440GX AGPset Platform Reference Design Ultra I/O Component 20 This page shows the Ultra I/O component. The RTC may optionally be used. An Infra Red Header Port is also optional. AGP Connector 21 This page shows the AGP connector. In this design, AGP INTA and INTB are connected to the PCI INTA and INTB through a buffer/driver. The interrupt signals are open-collector, and pulled up to VCC3.3. PCI Connectors 22-23 These pages show the PCI connectors. In this design, four PCI connectors are used.
Intel® 440GX AGPset Platform Reference Design Power Connectors Front Panel Jumpers 32 This page shows the system ATX power connector, hardware reset logic, and standard chassis connectors for the hard disk, power LEDs, and speaker output. Included on this page are the dualcolor LED circuit required to indicate the system state (either ON, OFF, or any of the suspend states), the 6-pin optional ATX connector, and the Wake-On-LAN header. Note: a CPU Fan Header is required for the Intel Boxed processor.