Update

R
Specification Update 15
Documentation Changes
1. Ball Definition for RSTIN# Incorrectly shown in Table 51
Table 51, “XOR Chain Exclusion List of Pins” incorrectly shows the ball definition for RSTIN# to be
D28. Actual ball definition is AD28. D28 is a VSS ball. This is the only reference where RSTIN# is
incorrectly defined. Ballout diagram in Section 11 is correct.
2.
DVODETECT Internal Resistor Is Improperly Defined in Section 3.6.3
The text in Section 3.6.3 Intel 855GME GMCH DVO/I2C to AGP Pin Mapping states:
“The GMCH has an internal 8.2-k, pull-up on this signal that will naturally pull it high. If an AGP
graphics device is present, the signal will be pulled low at the AGP graphics device and the AGP/DVO
mux select bit in the SHIC register will be set to AGP mode.”
Text should now read:
“The GMCH has an internal 8.2-k, pull-down on this signal that will naturally pull it low. If an AGP
graphics device is present, the signal will be pulled high at the AGP graphics device and the AGP/DVO
mux select bit in the SHIC register will be set to AGP mode.”
3.
Section 9.4 and Section 11 Incorrectly Show Some Signal Pins As Reserved
Section 9.4 Table 51 , Section 11 Figure 9, and Section 11 Table 58 show balls D2, D3, B3, F2, F3, L4
, and B2 as reserved. Balls should be defined as follows for the 855GME.
Ball Signal Name
D2 GWBF#
D3 GRBF#
B3 GREQ#
F2 GSBSTB
F3 GSBSTB#
L4 GCBE2#
B2 GGNT#