Uncore Manual

Reference Number: 329468-002 113
Uncore Performance Monitoring
Power Control (PCU) Performance Monitoring
The PCU performance monitor data registers are 48-bit wide. A counter overflow occurs when a carry
out from bit 47 is detected. Software can force all uncore counting to freeze after N events by
preloading a monitor with a count value of 2
48
- N and setting the control register to send an overflow
message to the UBox (refer to Section 2.1.1, “Counter Overflow”). During the interval of time
between overflow and global disable, the counter value will wrap and continue to collect events.
If accessible, software can continuously read the data registers without disabling event collection.
Table 2-122. PCU_MSR_PMON_CTR{3-0} Register – Field Definitions
Context sensitive filtering is provided for through the PCU_MSR_PMON_BOX_FILTER register.
• For frequency/voltage band filters, the multiplier is at 100MHz granularity. So, a value of 32
(0x20) would represent a frequency of 3.2GHz.
• Support for limited Frequency/Voltage Band histogramming. Each of the four bands provided for
in the filter may be simultaneous tracked by the corresponding event
NOTE
Since use of the register as a filter is heavily overloaded, simultaneous application of
this filter to additional events in the same run is severely limited.
occ_sel 15:14 RW-V 0 Select which of three occupancy counters to use.
01 - Cores in C0
10 - Cores in C3
11 - Cores in C6
rsv 13:8 RV 0 Reserved
ev_sel 7:0 RW-V 0 Select event to be counted.
NOTE: Bit 7 denotes whether the event requires the use of
an occupancy subcounter.
Field Bits Attr
HW
Reset
Val
Description
rsv 63:48 RV 0 Reserved
event_count 47:0 RW-V 0 48-bit performance event counter
Field Bits Attr
HW
Reset
Val
Description