Uncore Manual

Uncore Performance Monitoring
Power Control (PCU) Performance Monitoring
112 Reference Number: 329468-002
- .occ_invert - Changes the .thresh test condition to ‘<‘ for the occupancy events (when .ev_sel[7] is
set to 1)
- .occ_edge_det - Rather than accumulating the raw count each cycle (for events that can
increment by 1 per cycle), the register can capture transitions from no event to an event
incoming for the PCU’s occupancy events (when .ev_sel[7] is set to 1).
Table 2-121. PCU_MSR_PMON_CTL{3-0} Register – Field Definitions
Field Bits Attr
HW
Reset
Val
Description
occ_edge_det 31 RW-V 0 Enables edge detect for occupancy events (.ev_sel[7] is 1)
When set to 1, rather than measuring the event in each
cycle it is active, the corresponding counter will increment
when a 0 to 1 transition (i.e. rising edge) is detected.
When 0, the counter will increment in each cycle that the
event is asserted.
NOTE: .edge_det is in series following .thresh. Due to this,
the .thresh field must be set to a non-0 value. For events
that increment by no more than 1 per cycle, set .thresh to
0x1.
occ_invert 30 RW-V 0 Invert comparison against Threshold for the PCU
Occupancy events (.ev_sel[7] is 1)
0 - comparison will be ‘is event increment >= threshold?’.
1 - comparison is inverted - ‘is event increment <
threshold?’
NOTE: .invert is in series following .thresh. Due to this, the
.thresh field must be set to a non-0 value. For events that
increment by no more than 1 per cycle, set .thresh to 0x1.
Also, if .edge_det is set to 1, the counter will increment
when a 1 to 0 transition (i.e. falling edge) is detected.
rsv 29 RV 0 Reserved. SW must write to 0 else behavior is undefined.
thresh 28:24 RW-V 0 Threshold used in counter comparison.
rsv 23 RV 0 Reserved. SW must write to 0 else behavior is undefined.
en 22 RW-V 0 Local Counter Enable.
ev_sel_ext 21 RW-V 0 Extension bit to the Event Select field.
ov_en 20 RW-V 0 When this bit is asserted and the corresponding counter
overflows, its overflow bit is set in the local status register
(PCU_PMON_BOX_STATUS.ov) and an overflow is sent on
the message channel to the UBox. When the overflow is
received by the UBox, the bit corresponding to this PCU will
be set in U_MSR_PMON_GLOBAL_STATUS.ov_p.
rsv 19 RV 0 Reserved
edge_det 18 RW-V 0 When set to 1, rather than measuring the event in each
cycle it is active, the corresponding counter will increment
when a 0 to 1 transition (i.e. rising edge) is detected.
When 0, the counter will increment in each cycle that the
event is asserted.
NOTE: .edge_det is in series following .thresh. Due to this,
the .thresh field must be set to a non-0 value. For events
that increment by no more than 1 per cycle, set .thresh to
0x1.
rst 17 WO 0 When set to 1, the corresponding counter will be cleared to
0.
rsv 16 RV 0 Reserved