Specification Update


Intel
®
Core
™
i5-600, i3-500 Desktop Processor Series and
Intel
®
Pentium Desktop Processor 6000 Series
November 2014 Specification Update
Document Number: 322911-021US 9
Errata (Sheet 1 of 5)
Number
Steppings
Status ERRATA
C-2 K-0
AAU1
X X No Fix The Processor May Report a #TS Instead of a #GP Fault
AAU2
X X No Fix
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page
Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or
Lead to Memory-Ordering Violations
AAU3
X X No Fix
Code Segment Limit/Canonical Faults on RSM May Be Serviced before Higher
Priority Interrupts/Exceptions and May Push the Wrong Address onto the Stack
AAU4
X X No Fix Performance Monitor SSE Retired Instructions May Return Incorrect Values
AAU5
X X No Fix Premature Execution of a Load Operation Prior to Exception Handler Invocation
AAU6
X X No Fix MOV To/From Debug Registers Causes Debug Exception
AAU7
X X No Fix
Incorrect Address Computed for Last Byte of FXSAVE/FXRSTOR Image Leads
to Partial Memory Update
AAU8
X X No Fix Values for LBR/BTS/BTM Will Be Incorrect after an Exit from SMM
AAU9
X X No Fix Single Step Interrupts with Floating Point Exception Pending May Be Mishandled
AAU10
X X No Fix Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame
AAU11
X X No Fix
IRET under Certain Conditions May Cause an Unexpected Alignment Check
Exception
AAU12
X X No Fix
General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be
Preempted
AAU13
X X No Fix
General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit
Violation above 4-G Limit
AAU14
X X No Fix
LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt
Occurs in 64-bit Mode
AAU15
X X No Fix
MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB
Error
AAU16
X X No Fix
Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled
Breakpoints
AAU17
X X No Fix MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang
AAU18
X X No Fix
Corruption of CS Segment Register During RSM While Transitioning From Real
Mode to Protected Mode
AAU19
X X No Fix
Performance Monitoring Events for Read Miss to Level 3 Cache Fill Occupancy
Counter may be Incorrect
AAU20
X X No Fix A VM Exit on MWAIT May Incorrectly Report the Monitoring Hardware as Armed
AAU21
X X No Fix Performance Monitor Event SEGMENT_REG_LOADS Counts Inaccurately
AAU22
X X No Fix
#GP on Segment Selector Descriptor that Straddles Canonical Boundary May
Not Provide Correct Exception Error Code
AAU23
X X No Fix
Improper Parity Error Signaled in the IQ Following Reset When a Code
Breakpoint is Set on a #GP Instruction
AAU24
X X No Fix
An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/
POP SS Instruction if it is Followed by an Instruction That Signals a Floating
Point Exception
AAU25
X X No Fix IA32_MPERF Counter Stops Counting During On-Demand TM1