Specification Update

Intel
®
Core
™
i5-600, i3-500 Desktop Processor Series and
Intel
®
Pentium Desktop Processor 6000 Series
Specification Update November 2014
50 Document Number: 322911-021US
AAU109. Execution of VMPTRLD May Corrupt Memory If Current-VMCS Pointer
is Invalid
Problem: If the VMCLEAR instruction is executed with a pointer to the current-VMCS
(virtualmachine control structure), the current-VMCS pointer becomes invalid as
expected. A subsequent execution of the VMPTRLD (Load Pointer to Virtual-Machine
Control Structure) instruction may erroneously overwrite the four bytes at physical
address 0000008FH.
Implication: Due to this erratum, the four bytes in system memory at physical address 0000008FH
may be corrupted.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU110. PerfMon Overflow Status Can Not be Cleared After Certain Conditions
Have Occurred
Problem: Under very specific timing conditions, if software tries to disable a PerfMon counter
through MSR IA32_PERF_GLOBAL_CTRL (0x38F) or through the per-counter
eventselect (e.g. MSR 0x186) and the counter reached its overflow state very close to
that time, then due to this erratum the overflow status indication in MSR
IA32_PERF_GLOBAL_STAT (0x38E) may be left set with no way for software to clear it.
Implication: Due to this erratum, software may be unable to clear the PerfMon counter overflow
status indication.
Workaround: Software may avoid this erratum by clearing the PerfMon counter value prior to
disabling it and then clearing the overflow status indication bit.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU111. Intel
®
Trusted Execution Technology ACM Revocation
Problem: SINIT ACM i5_i7_DUAL_SINIT_18.BIN or earlier are revoked and will not launch with
new processor configuration information.
Implication: Due to this erratum, SINIT ACM i5_i7_DUAL_SINIT_18.BIN and earlier will be revoked.
Workaround: It is possible for the BIOS to contain a workaround for this erratum. All Intel® TXT
enabled software must use SINIT ACM i5_i7_DUAL_SINIT_51.BIN or later.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU112. The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not
Updated After a UC Error is Logged
Problem: When a UC (uncorrected) error is logged in the IA32_MC0_STATUS MSR (401H),
corrected errors will continue to update the lower 14 bits (bits 51:38) of the Corrected
Error Count. Due to this erratum, the sticky count overflow bit (bit 52) of the Corrected
Error Count will not get updated after a UC error is logged.
Implication: The Corrected Error Count Overflow indication will be lost if the overflow occurs after an
uncorrectable error has been logged.
Workaround: None identified
Status: For the steppings affected, see the Summary Tables of Changes.