Specification Update

Intel
®
Core
™
i5-600, i3-500 Desktop Processor Series and
Intel
®
Pentium Desktop Processor 6000 Series
Specification Update November 2014
48 Document Number: 322911-021US
AAU103. PCIe Port’s LTSSM May Not Transition Properly in the Presence of TS1
or TS2 Ordered Sets That Have Unexpected Symbols Within those Sets
Problem: When a PCIe port receives TS1 and/or TS2 ordered sets with unexpected symbols (per
the PCIe Base Specification), the port’s LTSSM (Link Training State Machine) might not
transition according to the PCIe Base Specification requirements. The LTSSM may
incorrectly stay in its current state, or transition to an incorrect state. If the unexpected
symbols are sporadic in nature the link will recover and go to the proper state.
Implication: PCIe Port’s LTSMM may not transition according to PCIe Base Specification as described
above. This problem has not been seen in real system testing, but was discovered by
synthetic tests designed to check for illegal conditions.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU104. NTB/RP Link Will Send Extra TS2 Ordered Set During Link Training
Problem: The NTB (Non-Transparent Bridge) when operating in NTB/RP (Root Port) mode will
send a superfluous TS2 ordered set after transitioning to the CONFIGURATION.IDLE
state during link training. This TS2 ordered set may contain invalid capability data.
Implication: NTB/RP Link will transmit a TS2 ordered set after transitioning to the
CONFIGURATION.IDLE state. No impact expected for specification compliant PCIe
partners. Specification compliant PCIe link partners will have transitioned to
CONFIGURATION.IDLE before this ordered set is sent and will ignore it.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU105. PCIe Ports May Not Enter Slave Loopback Mode From the
Configuration LTSSM State
Problem: If a PCIe port’s LTSSM (Link Training State Machine) is in the
CONFIG.LINK_WIDTH_START state, it may not enter slave loopback mode when
requested to do so by the link partner. If the request is missed the link will continue to
train and enter the Slave loopback mode after it first transitions through the L0 and
RECOVERY LTSSM states.
Implication: Due to this erratum, PCIe ports may be delayed in entering the slave loopback mode.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.