Specification Update


Intel
®
Core
™
i5-600, i3-500 Desktop Processor Series and
Intel
®
Pentium Desktop Processor 6000 Series
November 2014 Specification Update
Document Number: 322911-021US 47
AAU100. VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
Problem: If the “load IA32_PERF_GLOBAL_CTRL” VM-exit control is 1, a VM exit should load the
IA32_PERF_GLOBAL_CTRL MSR (38FH) from the IA32_PERF_GLOBAL_CTRL field in the
guest-state area of the VMCS. Due to this erratum, such a VM exit may instead clear
bits 34:32 of the MSR, loading only bits 31:0 from the VMCS.
Implication: All fixed-function performance counters will be disabled after an affected VM exit, even
if the VM exit should have enabled them based on the IA32_PERF_GLOBAL_CTRL field
in the guest-state area of the VMCS.
Workaround: A VM monitor that wants the fixed-function performance counters to be enabled after a
VM exit may do one of two things: (1) clear the “load IA32_PERF_GLOBAL_CTRL” VM-
exit control; or (2) include an entry for the IA32_PERF_GLOBAL_CTRL MSR in the VM-
exit MSR-load list.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU101. Correctable and Uncorrectable Cache Errors May be Reported Until the
First Core C6 Transition
Problem: On a subset of processors it is possible that correctable/uncorrectable cache errors may
be logged and/or a machine check exception may occur prior to the first core C6
transition. The errors will be logged in IA32_MC5_STATUS MSR (415H) with the
MCACOD (Machine Check Architecture Error Code) bits [15:0] indicating a Cache
Hierarchy Error of the form 000F 0001 RRRR TTLL.
Implication: Due to this erratum, correctable/uncorrectable cache error may be logged or signaled.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU102. Accesses to a VMCS May Not Operate Correctly If CR0.CD is Set on Any
Logical Processor of a Core
Problem: The VMX (virtual-machine extensions) are controlled by the VMCS (virtual-machine
control structure). If CR0.CD is set on any logical processor of a core, operations using
the VMCS may not function correctly. Such operations include the VMREAD and
VMWRITE instructions as well as VM entries and VM exits.
Implication: If CR0.CD is set on either logical processor in a core, the VMWRITE instruction may not
correctly update the VMCS and the VMREAD instruction may not return correct data.
VM entries may not load state properly and may not establish VMX controls properly.
VM exits may not save or load state properly.
Workaround: VMMs (Virtual-machine monitors) should ensure that CR0.CD is clear on all logical
processors of a core before entering VMX operation on any logical processor. Software
should not set CR0.CD on a logical processor if any logical processor of the same core is
in VMX operation. VMM software should prevent guest software from setting CR0.CD by
setting bit 30 in the CR0 guest/host mask field in every VMCS.
Status: For the steppings affected, see the Summary Tables of Changes.