Specification Update



Intel

Core

™

i5-600, i3-500 Desktop Processor Series and

Intel

Pentium Desktop Processor 6000 Series

November 2014 Specification Update

Document Number: 322911-021US 45

AAU93. VM Entry to 64-Bit Mode May Fail if Bits 48 And 47 of Guest RIP Are

Different

Problem: VM entry to 64-bit mode should allow any value for bits [47:0] of the RIP field in the

guest-state area as long as bits 63:48 are identical. Due to this erratum, such a VM

entry may fail if bit 47 of the field has a value different from that of bit 48.

Implication: It is not possible to perform VM entry to a 64-bit guest that has made a transition to a

non-canonical instruction pointer.

Workaround: It is possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

AAU94. VM Entry Loading an Unusable SS Might Not Set SS.B to 1

Problem: If the unusable bit (bit 16) is 1 in the guest SS (Stack Segment) access-rights field, VM

entry should set the B bit (default stack-pointer size) in the SS (stack segment)

guest SS access-rights field, potentially clearing SS.B to 0.

Implication: This erratum can affect software only if a far RET instruction is executed after a VM

entry that erroneously clears the B bit and only if the following other three conditions

are also true: (1) the SS register is not loaded between VM entry and far RET; (2) the

far RET instruction is executed in 64-bit mode with an immediate operand; (3) the far

RET instruction makes a transition to compatibility mode without changing CPL

(Current Privilege Level). Due to the far RET being executed with an immediate

operand, an adjustment is made to the stack pointer. Normally, when SS is unusable

the SS.B bit is 1 and the adjustment will be to the 32-bit ESP register. Due to this

erratum, the adjustment will incorrectly be made to the 16-bit SP register. Intel has not

observed this erratum with any commercially available software.

Workaround: It is possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

AAU95. FSW May Be Corrupted If an x87 Store Instruction Causes a Page Fault

in VMX Non-Root Operation

Problem: The X87 FSW (FPU Status Word) may be corrupted if execution of a floating-point store

instruction (FST, FSTP, FIST, FISTP, FISTTP) causes a page fault in VMX non-root

operation.

Implication: This erratum may result in unexpected behavior of software that uses x87 FPU

instructions.

Workaround: It is possible for the BIOS to contain a workaround for this erratum.

Status: None identified.