Specification Update

Intel
®
Core
™
i5-600, i3-500 Desktop Processor Series and
Intel
®
Pentium Desktop Processor 6000 Series
Specification Update November 2014
44 Document Number: 322911-021US
AAU89. PCI Express x16 Port Links May Fail to Dynamically Switch From
5.0GT/s to 2.5GT/s
Problem: If an endpoint device initiates a PCI Express speed change from 5.0 GT/s to 2.5 GT/s,
the link may incorrectly go into Recovery.Idle rather than the expected Recovery.Speed
state. This may cause the link to lose sync, eventually resulting in a link down. The link
will recover and re-train to the L0 state, however any outstanding packets queued
during the speed change may be lost.
Implication: Due to this erratum, the link may lose sync resulting in link down with queued packet
being lost. No known failures have been observed on systems using production PCI
Express graphics cards. This erratum has only been observed in a synthetic test
environment.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU90. PCI Express Cards May Not Train to x16 Link Width
Problem: The Maximum Link Width field in the Link Capabilities register (LCAP; Bus 0; Device 1;
Function 0; offset 0xAC; bits [9:4]) may limit the width of the PCI Express link to x8,
even though the processor may actually be capable of supporting the full x16 width.
Implication: PCI Express x16 Graphics Cards used in normal operation and PCI Express CLB
(Compliance Load Board) Cards used during PCI Express Compliance mode testing may
only train to x8 link width.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum
Status: For the steppings affected, see the Summary Tables of Changes.
AAU91. Unexpected Graphics VID Transition During Warm Reset May Cause
the System to Hang
Problem: During a warm reset to the processor, the graphics VID (Voltage ID) may transition to
an unexpected value that may cause the voltage regulator to shut off.
Implication: The processor may hang during integrated graphics initialization. Cold boots and
platforms using discrete graphics are not affected by this issue.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU92. IO_SMI Indication in SMRAM State Save Area May Be Lost
Problem: The IO_SMI bit (bit 0) in the IO state field at SMRAM offset 7FA4H is set to "1" by the
processor to indicate a System Management Interrupt (SMI) is either taken
immediately after a successful I/O instruction or is taken after a successful iteration of
a REP I/O instruction. Due to this erratum, the setting of the IO_SMI bit may be lost.
This may happen under a complex set of internal conditions with Intel® Hyper-
Threading Technology enabled and has not been observed with commercially available
software.
Implication: Due to this erratum, SMI handlers may not be able to identify the occurrence of I/O
SMIs.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.