Specification Update

Intel
®
Core
™
i5-600, i3-500 Desktop Processor Series and
Intel
®
Pentium Desktop Processor 6000 Series
Specification Update November 2014
12 Document Number: 322911-021US
AAU78
X X No Fix
If the APIC timer Divide Configuration Register (Offset 03E0H) is written at the
same time that the APIC timer Current Count Register (Offset 0390H) reads 1H,
it is possible that the APIC timer will deliver two interrupts.
AAU79
X Fixed TXT.PUBLIC.KEY is Not Reliable
AAU80
X Fixed
8259 Virtual Wire B Mode Interrupt May Be Dropped When it Collides With
Interrupt Acknowledge Cycle From the Preceding Interrupt
AAU82
X X No Fix
The APIC Timer Current Count Register May Prematurely Read 0x0 While the
Timer is Still Running
AAU83
X X No Fix Secondary PCIe Port May Not Train After A Warm Reset
AAU84
X X No Fix The PECI Bus May Be Tri-stated after System Reset
AAU85
X X No Fix
The Combination of a Page-Split Lock Access And Data Accesses That Are Split
Across Cacheline Boundaries May Lead to Processor Livelock
AAU86
X X No Fix Processor Hangs on Package C6 State Exit
AAU87
X X No Fix A Synchronous SMI May be Delayed
AAU88
X X No Fix
FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access
Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-
bit Mode
AAU89
X X Plan Fix
PCI Express x16 Port Links May Fail to Dynamically Switch From 5.0GT/s to
2.5GT/s
AAU90
X X No Fix PCI Express Cards May Not Train to x16 Link Width
AAU91
X X No Fix
Unexpected Graphics VID Transition During Warm Reset May Cause the System
to Hang
AAU92
X X No Fix IO_SMI Indication in SMRAM State Save Area May Be Lost
AAU93
X Fixed VM Entry to 64-Bit Mode May Fail if Bits 48 And 47 of Guest RIP Are Different
AAU94
X Fixed VM Entry Loading an Unusable SS Might Not Set SS.B to 1
AAU95
X Fixed
FSW May Be Corrupted If an x87 Store Instruction Causes a Page Fault in VMX
Non-Root Operation
AAU96
X X No Fix
Under Certain Low Temperature Conditions, Some Uncore Performance
Monitoring Events May Report Incorrect Results
AAU97
X X No Fix CKE May go Low Within tRFC(min) After a PD Exit
AAU98
X X No Fix
Erratum AAU98 added to this specification Update in error; all erratum details
removed from the specification update document.
AAU99
X X No Fix
Performance Monitor Events for Hardware Prefetches Which Miss The L1 Data
Cache May be Over-Counted
AAU100
X X No Fix VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
AAU101
X Fixed
Correctable and Uncorrectable Cache Errors May be Reported Until the First
Core C6 Transition
AAU102
X X No Fix
Accesses to a VMCS May Not Operate Correctly If CR0.CD is Set on Any Logical
Processor of a Core
AAU103
X X No Fix
PCIe Port’s LTSSM May Not Transition Properly in the Presence of TS1 or TS2
Ordered Sets That Have Unexpected Symbols Within those Sets
AAU104
X X No Fix NTB/RP Link Will Send Extra TS2 Ordered Set During Link Training
Errata (Sheet 4 of 5)
Number
Steppings
Status ERRATA
C-2 K-0