Datasheet

Register Description
R
Datasheet 99
3.7.30 AGPCTRL – AGP Control Register (Device #0)
Address Offset: B0–B1h
Default Value: 0000h
Access: Read/Write
Size: 16 bits
This register provides for additional control of the AGP interface.
Note: Bit 7 is visible to the operating system and must be retained in this position.
Bit Description
15:8 Reserved
7 GTLB Enable (and GTLB Flush Control).
NOTE: This bit can be changed dynamically (i.e., while an access to GTLB occurs).
This bit must not be changed through memory mapped configuration register access
space.
6:0 Reserved
3.7.31 AFT – AGP Functional Register (Device #0)
Address Offset: B2–B3h
Default Value: E9F0h
Access: Read/Write, Read/WriteClear
Size: 16 bits
This register provides for additional control of the AGP interface.
Bit Description
15:11 Reserved
10 PCI Write Streaming Disable (PCIBWSD): When this bit is set to ‘1’, PCI_B writes to
DDR SDRAM are disconnected at a 32 byte cache line boundary (write streaming is
disabled). When this bit is set to ‘0’ (default), write streaming is enabled.
9:0 Reserved