Datasheet

94 Datasheet

Bit Description

4:2 Reserved

1 SERR on Multiple-bit ECC Error:

1 = For systems that support ECC, this field must be set to 1.

0 = Reserved

0 SERR on Single-bit ECC Error:

1 = For systems that support ECC, this field must be set to 1.

0 = Reserved

3.7.24 SMICMD – SMI Error Command Register (Device #0)

Address Offset: 66h

Default Value: 00h

Access: Read/Write

Size: 8 bits

This register enables various errors to generate an SMI cycle. When an Error Flag is set in the

ERRSTS register, it can generate a SERR or SMI cycle when enabled in the ERRCMD,

SMICMD, or SCICMD registers respectively. An error can generate one and only one Error

cycle. It is software’s responsibility to make sure that when an SMI Error Message is enabled for

an error condition, SERR, and SCI Error Messages are disabled for that same error condition.

Bit Description

7:4 Reserved

3 SMI on GMCH/MCH Thermal Sensor Trip:

1 = An SMI Hub Interface Special cycle is generated by GMCH/MCH when the Thermal

Sensor Trip requires an SMI. A Thermal Sensor Trip Point cannot generate more

than one special cycle.

2 Reserved

1 SMI on Multiple-bit ECC Error:

1 = For systems that support ECC, this field must be set to 1.

0 = Reserved

0 SMI on Single-bit ECC Error:

1 = For systems that support ECC, this field must be set to 1.

0 = Reserved