Datasheet

Register Description
R
Datasheet 93
3.7.23 ERRCMD – Error Command Register (Device #0)
Address Offset: 64–65h
Default Value: 0000h
Access: Read/Write
Size: 16 bits
This register enables various errors to generate. The actual generation of the SERR message is
globally enabled for Device #0 via the PCI Command register. It is software’s responsibility to
make sure that when an SERR error message is enabled for an error condition, SMI and SCI error
messages are disabled for that same error condition.
Bit Description
15:14 Reserved
13 SERR on FSB Strobe Glitch: When this bit is asserted, the GMCH/MCH will generate a
SERR message when a glitch is detected on one of the FSB strobes.
12 Reserved
11 SERR on GMCH/MCH Thermal Sensor Event:
1 = The GMCH/MCH generates a SERR cycle on a Thermal Sensor Trip that requires
an SERR. The SERR must not be enabled at the same time as the SMI/SCI for a
Thermal Sensor Trip event.
0 = Software must Write a 1 to clear this status bit.
10 Reserved
9 SERR on LOCK to non-DDR SDRAM Memory:
1 = The GMCH/MCH generates an SERR cycle when a CPU initiated LOCK
transaction targeting non-DDR SDRAM Memory Space occurs.
0 = Reporting of this condition is disabled.
8 SERR on DDR SDRAM Refresh timeout:
1 = The GMCH/MCH generates an SERR cycle when a DDR SDRAM Refresh timeout
occurs.
0 = Reporting of this condition is disabled.
7 SERR on DDR SDRAM Throttle Condition:
1 = The GMCH/MCH generates an SERR cycle when a DDR SDRAM Read or Write
Throttle condition occurs.
0 = Reporting of this condition is disabled.
6 SERR on Receiving Target Abort on Hub Interface:
1 = The GMCH/MCH generates an SERR cycle when a GMCH/MCH cycle is
terminated with a Target Abort.
0 = Reporting of this condition is disabled.
5 SERR on Receiving Unimplemented Special Cycle Completion Packet:
1 = The GMCH/MCH generates an SERR cycle when a GMCH/MCH initiated request is
terminated with a Unimplemented Special cycle completion packet.
0 = Reporting of this condition is disabled.