Datasheet

Register Description
R
92 Datasheet
3.7.22 ERRSTS – Error Status Register (Device #0)
Address Offset: 62–63h
Default Value: 0000h
Access: Read/Write Clear
Size: 16 bits
This register is used to report various error conditions. A SERR or SMI cycle may be generated
on a zero to one transition of any of these flags when enabled in the PCICMD/ERRCMD,
SMICMD, or SCICMD registers respectively.
Bit Description
15:14 Reserved
13 FSB Strobe Glitch Detected (PSBAGL): When this bit is set to 1 the GMCH/MCH has
detected a glitch on one of the FSB strobes. Writing a 1 to it clears this bit.
12 GMCH/MCH Software Generated Event for SMI:
1 = This indicates the source of the SMI was a Device #2 Software Event.
0 = Software must Write a 1 to clear this bit.
11 GMCH/MCH Thermal Sensor Event for SMI/SCI/SERR:
1 = Indicates that a GMCH/MCH Thermal Sensor trip has occurred and an SMI, SCI or
SERR has been generated. Note that the status bit is set only if a message is sent
based on Thermal event enables in Error Command, SMI Command and SCI
Command registers. Note that a Trip Point can generate one of SMI, SCI or SERR
interrupts (two or more per event is illegal). Multiple Trip Points can generate the
same interrupt. If software chooses this mode, then subsequent Trips may be lost.
0 = Software must Write a 1 to clear this status bit. If this bit is set, then an interrupt
message will not be sent on a new Thermal Sensor event.
10 Reserved
9 LOCK to non-DDR SDRAM Memory Flag (LCKF)—R/WC:
1 = Indicates that a CPU initiated LOCK cycle targeting non-DDR SDRAM Memory
Space occurred.
0 = Software must Write a 1 to clear this status bit
8 Received Refresh Timeout—R/WC:
1 = This bit is set when 1024 memory core refresh are Queued up.
0 = Software must Write a 1 to clear this status bit.
7 DRAM Throttle Flag (DTF)—R/WC:
1 = Indicates that the DDR SDRAM Throttling condition occurred.
0 = Software must Write a 1 to clear this status bit.
6:0 Reserved