Datasheet

R
Datasheet 9
Tables
Table 1. SDRAM Memory Capacity.................................................................................. 22
Table 2. Intel
®
852GME GMCH Interface Clocks .............................................................25
Table 3. Host Interface Signal Descriptions...................................................................... 28
Table 4. DDR SDRAM Interface Descriptions ..................................................................31
Table 5. AGP Addressing Signal Descriptions ................................................................. 33
Table 6. AGP Flow Control Signals .................................................................................. 34
Table 7. AGP Status Signal Descriptions .........................................................................35
Table 8. AGP Strobe Descriptions.................................................................................... 36
Table 9. AGP/PCI Signals-Semantics Descriptions..........................................................37
Table 10. Hub Interface Signals........................................................................................39
Table 11. Clock Signals .................................................................................................... 40
Table 12. Dedicated LVDS Panel Interface Signal Descriptions...................................... 42
Table 13. Digital Video Port B Signal Descriptions...........................................................43
Table 14. Digital Video Port C Signal Descriptions........................................................... 44
Table 15. DVOB and DVOC Port Common Signal Descriptions...................................... 45
Table 16. Intel
®
852GME GMCH AGP/DVO Pin Muxing.................................................. 46
Table 17. Analog Display Signal Descriptions.................................................................. 47
Table 18. Graphics GPIO Signal Descriptions.................................................................. 48
Table 19. Voltage References, PLL Power....................................................................... 50
Table 20. Full and Warm Reset Waveforms.....................................................................53
Table 21. Host Signal Reset and Power Managed States ...............................................54
Table 22. System Memory Signal Reset and Power Managed States.............................55
Table 23. Hub Interface Signal Reset and Power Managed States ................................. 56
Table 24. GMCH DVO Signal Reset and Power Managed States...................................57
Table 25. GMCH GPIO Signal Reset and Power Managed States..................................60
Table 26. GMCH LVDS Signal Reset and Power Managed States .................................61
Table 27. Device Number Assignment ............................................................................. 64
Table 28. Assignment Nomenclature for Access Attributes .............................................64
Table 29. GMCH/MCH Configuration Space - Device #0, Function#0............................. 71
Table 30. Attribute Bit Assignment....................................................................................86
Table 31. PAM Registers and Associated System Memory Segments............................88
Table 32. Host-Hub interface Bridge/System Memory Controller Configuration Space
(Device #0, Function#1)...........................................................................................104
Table 33. Configuration Process Configuration Space (Device#0, Function #3) ...........126
Table 34. Intel
®
852GME GMCH and Intel
®
852PM MCH Configurations .....................133
Table 35. Device 1 is the Virtual PCI to AGP Bridge (Device #1, Function #0)) ............ 134
Table 36. Integrated Graphics Device Configuration Space (Device #2, Function#0)...149
Table 37. System Memory Segments and Their Attributes ............................................164
Table 38. Pre-allocated System Memory........................................................................166
Table 39. SMM Space Transaction Handling .................................................................171
Table 40. Relation of DBI Bits to Data Bits .....................................................................177
Table 41. Data Bytes on SO-DIMM Used for Programming DDR SDRAM Registers ...179
Table 42. Dual Display Usage Model .............................................................................190
Table 43. Display Configuration Space ..........................................................................198
Table 44. Display Configuration Space ..........................................................................199
Table 45. Fast Write Initialization.................................................................................... 202
Table 46. PCI Commands Supported by the GMCH/MCH When Acting as a FRAME#
Target....................................................................................................................... 202
Table 47. Enhanced Intel SpeedStep
®
Technology Overview........................................206
Table 48. Absolute Maximum Ratings ............................................................................209