Datasheet

Register Description
R
86 Datasheet
Table 30. Attribute Bit Assignment
Bits [7, 3]
Reserved
Bits [6, 2]
Reserved
Bits [5, 1]
WE
Bits [4, 0]
RE
Description
X X 0 0 Disabled. DDR SDRAM is disabled and all
accesses are directed to hub interface. The
GMCH/MCH does not respond as a hub
interface target for any Read or Write access
to this area.
X X 0 1 Read Only. Reads are forwarded to DDR
SDRAM and Writes are forwarded to hub
interface for termination. This Write protects
the corresponding DDR SDRAM segment.
The GMCH/MCH will respond as a hub
interface target for Read accesses but not for
any Write accesses.
X X 1 0 Write Only. Writes are forwarded to DDR
SDRAM and Reads are forwarded to the hub
interface for termination. The GMCH/MCH will
respond as a hub interface target for Write
accesses but not for any Read accesses.
X X 1 1 Read/Write. This is the normal operating
mode of main system memory. Both Read
and Write cycles from the host are claimed by
the GMCH/MCH and forwarded to DDR
SDRAM. The GMCH/MCH will respond as a
hub interface target for both Read and Write
accesses.
As an example, consider a BIOS that is implemented on the Expansion bus. During the
initialization process, the BIOS can be shadowed in main system memory to increase the system
performance. When BIOS is shadowed in main system memory, it should be copied to the same
address location. To shadow the BIOS, the attributes for that address range should be set to Write
Only. The BIOS is shadowed by first doing a Read of that address. This Read is forwarded to the
Expansion bus. The Host then does a Write of the same address, which is directed to main system
memory. After the BIOS is shadowed, the attributes for that system memory area are set to Read
Only so that all Writes are forwarded to the Expansion bus. Figure 6 and Table 36 show the PAM
registers and the associated attribute bits.