Datasheet

Register Description
R
78 Datasheet
3.7.9 APBASE – Aperture Base Configuration (Device #0)
Address Offset: 10h
Default Value: 00000008h
Access: Read Only, Read/Write
Size: 32 bits
The APBASE is a standard PCI Base Address register that is used to set the base of the Graphics
Aperture. The standard PCI Configuration mechanism defines the base address configuration
register such that only a fixed amount of space can be requested (dependent on which bits are
hardwired to “0” or behave as hardwired to “0”). To allow for flexibility (of the aperture), an
additional register called APSIZE controls bits of the APBASE that behave as hardwired to “0” to
keep the aperture size aligned. This register is programmed by the GMCH/MCH specific BIOS
code before any of the generic configuration software runs.
Note: Bit 1 of the register 51h is used to prevent accesses to the aperture range before this register is
initialized and the appropriate translation table structure has been established in the main memory.
Bit Description
31:28 Upper Programmable Base Address (UPBITS): Upper Programmable Base Address bits—
R/W. These bits are used to locate the range size selected via lower bits 27:25. Default =
0000
27:22 Lower “Hardwired”/Programmable Base Address bits (LOBITS): These bits behave as
“hardwired” or as a programmable depending on the contents of the APSIZE register as
defined below:
27 26 Aperture Size
r/w r/w 64 MB
r/w 0 128 MB
0 0 256 MB
Bits 25:22 = 0, enforcing a minimum aperture size to 64 MB.
If AGP Capability in CAPREG is intact (“0”) then:
Bits 27:26 are controlled by the bits 5:4 of the APSIZE register in the following manner:
If bit APSIZE[5]=0 then APBASE[27]=0 and if APSIZE[5]=1 then APBASE[27]=r/w
(read/write).
21:4 Lower Bits (LOWBITS): These bits are 0.
3 Prefetchable (PF): This bit is 1 to identify the Graphics Aperture range as a prefetchable as
per the PCI specification for base address registers. This implies that there are no side
effects on reads, the device returns all bytes on reads regardless of the byte enables, and the
GMCH/MCH may merge processor writes into this range without causing errors.
2:1 Addressing Type (TYPE): These bits determine addressing type and they are hardwired to
00 to indicate that address range defined by the upper bits of this register can be located
anywhere in the 32-bit address space as per the PCI specification for base address registers.
0 Memory Space Indicator (MSPACE): This bit is 0 and is used to identify the aperture range
as a memory range as per the specification for PCI base address registers.