Datasheet

74 Datasheet

3.7.3 PCICMD – PCI Command Register (Device #0)

Address Offset: 04-05h

Default Value: 0006h

Access: Read Only, Read/Write

Size: 16 bits

Since GMCH/MCH Device #0 does not physically reside on PCI_A many of the bits are not

implemented.

Bit Description

15:10 Reserved

9 Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do fast

back-to-back Write. Since Device #0 is strictly a target, this bit is not implemented and is

hardwired to 0. Writes to this bit position have no affect.

SERR Enable (SERRE): This bit is a global enable bit for Device #0 SERR messaging. The

GMCH/MCH does not have an SERR# signal, but communicates the SERR# condition by

sending an SERR message to the ICH4-M.

1 = Enable. GMCH/MCH is enabled to generate SERR messages over hub interface for

specific Device #0 error conditions that are individually enabled in the ERRCMD register. The

error status is reported in the ERRSTS and PCISTS registers.

0 = SERR message is not generated by the GMCH/MCH for Device #0.

NOTE: This bit only controls SERR messaging for the Device #0. Device #1 has its own SERRE

bit to control error reporting for error conditions occurring on Device #1. The two control bits are

used in a logical OR manner to enable the SERR hub interface message mechanism.

7 Address/Data Stepping Enable (ADSTEP): Address/data stepping is not implemented in the

GMCH/MCH, and this bit is hardwired to 0. Writes to this bit position have no effect.

6 Parity Error Enable (PERRE): PERR# is not implemented by GMCH/MCH and this bit is

hardwired to 0. Writes to this bit position have no effect.

5 VGA Palette Snoop Enable (VGASNOOP): The GMCH/MCH does not implement this bit and it

is hardwired to a 0. Writes to this bit position have no effect.

4 Memory Write and Invalidate Enable (MWIE): The GMCH/MCH will never issue memory write

and invalidate commands. This bit is therefore hardwired to 0. Writes to this bit position will have

no effect.

3 Special Cycle Enable (SCE): The GMCH/MCH does not implement this bit and it is hardwired to

a 0. Writes to this bit position have no effect.

2 Bus Master Enable (BME): The GMCH/MCH is always enabled as a master on hub interface.

This bit is hardwired to a 1. Writes to this bit position have no effect.

1 Memory Access Enable (MAE): The GMCH/MCH always allows access to main system

memory. This bit is not implemented and is hardwired to 1. Writes to this bit position have no

effect.

0 I/O Access Enable (IOAE): This bit is not implemented in the GMCH/MCH and is hardwired to a

0. Writes to this bit position have no effect.