Datasheet

Register Description
R
68 Datasheet
DDR SDRAM configurations, operating parameters, and optional system features that are
applicable and to program the GMCH/MCH registers accordingly.
3.6 I/O Mapped Registers
The GMCH/MCH contains two registers that reside in the CPU I/O Address Space: the
Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data
(CONFIG_DATA) Register. The Configuration Address Register enables/disables the
Configuration Space and determines what portion of Configuration Space is visible through the
Configuration Data window.
3.6.1 CONFIG_ADDRESS – Configuration Address Register
I/O Address: 0CF8h Accessed as a Dword
Default Value: 00000000h
Access: Read/Write
Size: 32 bits
CONFIG_ADDRESS is a 32-bit register that can be accessed only as a Dword. A Byte or Word
reference will “pass through” the Configuration Address register and the hub interface, onto the
PCI bus as an I/O cycle. The CONFIG_ADDRESS register contains the Bus Number, Device
Number, Function Number, and Register Number for which a subsequent configuration access is
intended.
Figure 4. Configuration Address Register
R
1 0
27811151623 24 30 31 10
R
0 0 0 0
0
Reserved
Register Number
Function Number
Device Number
Bus Number
Reserved
Enable
Bit
Default