Datasheet

Datasheet 67

Note: Although initial AGP platform implementations will not support hierarchical buses residing

below AGP, this specification still must define this capability in order to support PCI-66

compatibility. Note also that future implementations of the AGP devices may support hierarchical

PCI or AGP-like buses coming out of the root AGP device.

3.5 Register Definitions

The GMCH/MCH contains four sets of software accessible registers accessed via the Host CPU

I/O Address Space, and they are as follows:

Control registers: I/O Mapped into the CPU I/O Space, which control access to PCI and AGP

Configuration Space via Configuration Mechanism #1 in the PCI 2.2 specification.

Internal Configuration registers: residing within the GMCH/MCH, they are partitioned into

three logical device register sets (“logical” since they reside within the single physical device).

• The first register set is dedicated to Host-HI Bridge functionality (i.e. DDR SDRAM

configuration, other chip-set operating parameters and optional features).

• The second register block is dedicated to Host-AGP/PCI_B Bridge functions (controls

AGP/PCI_B interface configurations and operating parameters).

• The third register block is for the integrated graphics functions.

Internal Memory Mapped Configuration registers: reside in the GMCH/MCH Device #0.

Internal Memory Mapped Configuration registers and Legacy VGA registers: reside in

the GMCH Device #2 that controls the Integrated Graphics Controller

The GMCH/MCH internal registers (I/O Mapped and Configuration registers) are accessible by

the Host CPU. The registers can be accessed as Byte, Word (16-bit), or Dword (32-bit) quantities,

with the exception of CONFIG_ADDRESS, which can only be accessed as a Dword. All multi-

byte numeric fields use “Little Endian Byte Ordering” (i.e., lower addresses contain the least

significant parts of the field).

Reserved Bits

Some of the GMCH/MCH registers described in this section contain Reserved bits. These bits are

labeled “Reserved”. Software must deal correctly with fields that are Reserved. On Reads,

software must use appropriate Masks to extract the defined bits and not rely on Reserved bits

being any particular value. On Writes, software must ensure that the values of Reserved bit

positions are preserved. That is, the values of Reserved bit positions must first be Read, Merged

with the new values for other bit positions and then Written back.

Note: The software does not need to perform Read, Merge, and Write operations for the Configuration

Address register.

Default Value Upon Reset

Upon a Full Reset, the GMCH/MCH set all of its Internal Configuration registers to a

predetermined default state. Some register values at Reset are determined by external strapping

options. The default state represents the minimum functionality feature set required to

successfully bring up the system. Hence, it does not represent the optimal system configuration. It

is the responsibility of the system initialization software (usually BIOS) to properly determine the